Low voltage avalanche photodiode with re-entrant mirror for silicon based photonic integrated circuits

• US 9,761,746 B2
• Filed: 03/11/2013
• Issued: 09/12/2017
• Est. Priority Date: 03/11/2013
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Kang, Yimin, Liu, Han-Din D., Liu, Ansheng
• Primary Examiner(s): Rizkallah, Kimberly
• Assistant Examiner(s): Turner, Brian
• Application Number:
  US13/976,369
• Publication Number:
  US 20140252411A1
• Time in Patent Office: 1,646 Days
• Field of Search: 257233, 257436, 257616, 257432, 257E25032, 385129, 385131
• CPC Class Codes: G02B 6/12007 forming wavelength selective elements, e.g. multiplexer, demultiplexer
• CPC Class Codes: G02B 6/122 Basic optical elements, e.g. light-guiding paths
• CPC Class Codes: G02B 6/131 by using epitaxial growth epitaxial growth for semiconductors H01L21/02365
• CPC Class Codes: G02B 6/30 for use between fibre and thin-film device
• CPC Class Codes: H01L 31/02327 the optical elements being integrated or being directly associated to the device, e.g. back reflectors optical coatings H01L31/0216
• CPC Class Codes: H01L 31/028 including, apart from doping material or other impurities, only elements of Group IV of the Periodic Table
• CPC Class Codes: H01L 31/105 the potential barrier being of the PIN type
• CPC Class Codes: H01L 31/107 the potential barrier working in avalanche mode, e.g. avalanche photodiodes
• CPC Class Codes: H01L 31/1075 in which the active layers, e.g. absorption or multiplication layers, form an heterostructure, e.g. SAM structure
• CPC Class Codes: H01L 31/1804 comprising only elements of Group IV of the Periodic Table
• CPC Class Codes: Y02E 10/547 Monocrystalline silicon PV cells

Abstract

A low voltage APD is disposed at an end of a waveguide extending laterally within a silicon device layer of a PIC chip. The APD is disposed over an inverted re-entrant mirror co-located at the end of the waveguide to couple light by internal reflection from the waveguide to an under side of the APD. In exemplary embodiments, a 45°-55° facet is formed in the silicon device layer by crystallographic etch. In embodiments, the APD includes a silicon multiplication layer, a germanium absorption layer over the multiplication layer, and a plurality of ohmic contacts disposed over the absorption layer. An overlying optically reflective metal film interconnects the plurality of ohmic contacts and returns light transmitted around the ohmic contacts to the absorption layer for greater detector responsivity.

Claims

1. A photonic integrated circuit (PIC), comprising:

an optical waveguide extending laterally in a crystalline silicon device layer and terminating at an end facet that is re-entrant from a top portion of the device layer;

a dielectric layer disposed over the device layer; and

an avalanche photodiode (APD) comprising

an n-type doped region embedded within the top portion of the device layer;

a silicon i-layer disposed over the n-type doped region;

a p-type silicon layer disposed over the i-layer;

a crystalline germanium layer disposed over the p-type silicon layer; and

a p-type doped semiconductor layer disposed over the germanium layer, wherein at least a portion of the re-entrant end facet is recessed below at least a portion of the embedded n-type doped region, wherein the APD futher comprises

a plurality of first metal contacts disposed over, and electrically coupled to, the p-type doped semiconductor layer, wherein the dielectric layer is disposed between adjacent ones of the first metal contacts; and

a metal sheet disposed over the dielectric layer and extending continuously between, and electrically interconnecting, the first metal contacts, wherein the metal sheet spans at least a majority of the area of the APD and is of a metal having a higher reflectivity than that of the first metal contacts within the wavelength band of the APD.

2. The PIC of claim 1, wherein the end facet has an index contrast with an interfacing material sufficient for the crystal plane to induce internal reflection of an optical mode propagated by the waveguide and redirect the mode into the germanium layer, and wherein the metal sheet has sufficient reflectivity to reflect light back through the germanium layer.

3. The PIC of claim 1, further comprising a second metal contact coupled to the n-type doped region and disposed adjacent to a side of the p-type silicon layer opposite the end facet.

4. The PIC of claim 1, wherein the device layer is 10-30 μ

m thick, is disposed over a thin film dielectric layer, and has {100} crystallinity, wherein a {100} or {110} crystal plane of the device layer forms the end facet, and wherein the i-layer is 0.07-0.13 μ

m thick.

5. The PIC of claim 4, wherein the end facet is one side of a recess etched into the device layer, the recess having a plurality of sides defined by a plurality of {110} or {100} crystal planes.

6. The PIC of claim 4, wherein at least majority of the APD is disposed directly over the recess etched end facet.

7. The PIC of claim 4, wherein the p-type Si layer is about 20 nm thick with a doping concentration between about 2×

10¹⁸ cm<sup>−

3</sup> to 3×

10¹⁸ cm <sup>−

3</sup>, and wherein the i-layer is 70-130 nm thick and with a doping concentration no more than 5×

10¹⁵ cm<sup>−

3</sup> .

8. The PIC of claim 1, wherein the waveguide further comprises a second end facet that is also re-entrant from the top portion of the device layer, wherein a {110} crystal plane of the device layer forms the second end facet.

9. The PIC of claim 1, wherein the dielectric layer is disposed on at least a portion of each of the p-type doped semiconductor layer, the n-type doped region, and the silicon i-layer.

10. The PIC of claim 1, wherein the APD is disposed over the waveguide forming a spacing between the APD and the end facet.

11. The PIC of claim 10, wherein a size of the spacing depends at least on one of a thickness of the waveguide and an angle of the end facet.

12. The PIC of claim 1, wherein the silicon i-layer has a crystallinity that follows a crystallinity of the device layer.

13. The PIC of claim 1, wherein the p-type silicon layer has a crystallinity that follows a crystallinity of the silicon i-layer.

14. A photonic integrated circuit (PIC),comprising:

an optical waveguide extending laterally in a crystalline silicon device layer and terminating at an end facet that is re-entrant from a top portion of the device layer;

a dielectric layer disposed over the device layer; and

an avalanche photodiode (APD) comprising

an n-type doped region embedded within the top portion of the device layer;

a silicon i-layer disposed over the n-type doped region;

a p-type silicon layer disposed over the i-layer;

a crystalline germanium layer disposed over the p-type silicon layer; and

a p-type doped semiconductor layer disposed over the germanium layer, wherein at least a portion of the re-entrant end facet is recessed below at least a portion of the embedded n-type doped region, wherein the p-type silicon layer has a crystallinity that follows a crystallinity of the device layer; and

an occlusion layer to seal opposite sides of the recess.

15. A photonic integrated circuit (PIC), comprising:

an optical waveguide extending laterally in a crystalline silicon device layer and terminating at an end facet that is re-entrant from a top surface of the device layer;

a dielectric layer disposed over the device layer;

an avalanche photodiode (APD) disposed over an n-type doped region of a top portion of the device layer, the APD including

a silicon i-layer disposed over the n-type doped region;

a p-type silicon layer disposed over the i-layer;

a crystalline germanium layer disposed over the p-type silicon layer; and

a p-type doped semiconductor layer disposed over the germanium layer, wherein at least a portion of the re-entrant end facet is recessed below at least a portion of the n-type doped region;

a plurality of first metal contacts disposed over, and electrically coupled to, the p-type doped semiconductor layer, wherein a dielectric material is disposed between adjacent ones of the first metal contacts,

a metal sheet disposed over the dielectric material and extending continuously between, and electrically interconnecting, the first metal contacts; and

a second metal contact coupled to the n-type doped region and disposed adjacent to a side of the p-type silicon layer opposite the end facet,

wherein the second metal contact passes through the dielectric layer to couple to a more heavily doped portion of the n-type doped region.