Frequency synthesizer and method controlling frequency synthesizer
First Claim
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1. A frequency synthesizer comprising:
- an oscillator configured to generate an oscillation frequency corresponding to a first channel code comprising a first plurality of bit values;
a frequency decider configured to;
(i) determine a bit value among the first plurality of bit values for the first channel code by comparing an output value corresponding to the oscillation frequency and a reference value corresponding to a target frequency,(ii) perform an error correction on the determined bit value by comparing a different value between the output value and the reference value with a predetermined stage range value, andrepeatedly perform (i) and (ii) until all of a second plurality of bit values for a second channel code are determined; and
a phase locker configured to fine tune, based on the second channel code, the oscillation frequency to the target frequency.
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Abstract
A voltage controlled oscillator (VCO) in a frequency synthesizer generates an output signal having a target frequency by being coarse tuned in accordance with a channel code derived through a binary tree search. Thereafter, the output signal of the VCO may be further tuned using a phase lock loop (PLL) circuit. Each stage of the binary tree search includes a comparison step that determines a channel code bit, and another step that confirms that the channel code converges to a final channel code within an established stage range value.
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Citations
18 Claims
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1. A frequency synthesizer comprising:
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an oscillator configured to generate an oscillation frequency corresponding to a first channel code comprising a first plurality of bit values; a frequency decider configured to; (i) determine a bit value among the first plurality of bit values for the first channel code by comparing an output value corresponding to the oscillation frequency and a reference value corresponding to a target frequency, (ii) perform an error correction on the determined bit value by comparing a different value between the output value and the reference value with a predetermined stage range value, and repeatedly perform (i) and (ii) until all of a second plurality of bit values for a second channel code are determined; and a phase locker configured to fine tune, based on the second channel code, the oscillation frequency to the target frequency. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12)
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13. A frequency synthesizer providing an output signal having a target frequency, the frequency synthesizer comprising:
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a voltage control oscillator (VCO) configured to generate the output signal; a first tuning loop configured to course tune the output signal to an intermediate frequency in response to a channel code selected on the basis of the target frequency, wherein the first tuning loop is configured to correct an error in a determination of the channel code during the coarse tuning using a channel code decider configured to determine the channel code by using a binary tree search, and the error correction in the determination of the channel code is performed with reference to a stage range for each stage of the binary tree search; and a second tuning loop configured to fine tune the output signal from the intermediate frequency to the target frequency based on completion of the first tuning loop. - View Dependent Claims (14, 15, 16)
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17. A frequency synthesizer comprising:
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a voltage controlled oscillator (VCO) configured to generate frequencies including a plurality of intermediate frequencies, wherein the plurality of intermediate frequencies correspond one-for-one with a plurality of channel codes; a frequency decider configured to upon receiving an instruction identifying a target frequency for the VCO, control a coarse tuning step of the VCO, such that the VCO generates an output signal having a desired intermediate frequency among the plurality of intermediate frequencies, wherein the coarse tuning step generates a comparison signal by comparing a reference value corresponding to the target frequency and an output signal indicative of the output signal and generates a correction signal by determining whether a difference value between the reference value and the output value exceeds a stage range value, such that the frequency decider traverses a binary search tree generated in accordance with the plurality of channel codes in response to the comparison signal and the correction signal. - View Dependent Claims (18)
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Specification