Stable probing-resilient physically unclonable function (PUF) circuit
First Claim
1. A physically unclonable function (PUF) circuit comprising:
- a clock terminal to receive a clock signal;
a PUF cell coupled to the clock terminal to receive the clock signal, the PUF cell to perform multiple instances of a bit generation process, responsive to the clock signal, to generate respective output bits at a bit node of the PUF cell; and
a counter coupled to the bit node to count a number of instances for which the output bit has a first logic value, wherein a value of a PUF bit associated with the PUF cell is based on the counted number.
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Abstract
Embodiments include apparatuses, methods, and systems for a physically unclonable function (PUF) circuit. The PUF circuit may include an array of PUF cells to generate respective PUF bits of an encryption code. Individual PUF cells may include first and second inverters cross-coupled between a bit node and a bit bar node. The individual PUF cells may further include a first pre-charge transistor coupled to the bit node and configured to receive a clock signal via a first clock path, and a second pre-charge transistor coupled to the bit bar node and configured to receive the clock signal via a second clock path. Features and techniques of the PUF cells are disclosed to improve the stability and/or bias strength of the PUF cells, to generate a dark bit mask for the array of PUF cells, and to improve resilience to probing attacks. Other embodiments may be described and claimed.
32 Citations
24 Claims
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1. A physically unclonable function (PUF) circuit comprising:
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a clock terminal to receive a clock signal; a PUF cell coupled to the clock terminal to receive the clock signal, the PUF cell to perform multiple instances of a bit generation process, responsive to the clock signal, to generate respective output bits at a bit node of the PUF cell; and a counter coupled to the bit node to count a number of instances for which the output bit has a first logic value, wherein a value of a PUF bit associated with the PUF cell is based on the counted number. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A physically unclonable function (PUF) circuit comprising a PUF cell that includes:
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a first inverter and a second inverter that are cross-coupled between a bit node and a bit bar node; a first pre-charge transistor coupled to the bit node, the first pre-charge transistor to receive a clock signal via a first clock path; and a second pre-charge transistor coupled to the bit bar node, the second pre-charge transistor to receive the clock signal via a second clock path; wherein the first and second clock paths include a first metal layer that is coupled to a clock terminal to receive the clock signal, and wherein the bit node and the bit bar node are disposed in a second metal layer that is below the first metal layer. - View Dependent Claims (12, 13, 14, 15, 16)
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17. A computer system comprising:
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a processor; a memory; a physically unclonable function (PUF) circuit coupled to the processor or the memory, the PUF circuit comprising; a first inverter and a second inverter that are cross-coupled between a bit node and a bit bar node; a first pre-charge transistor coupled to the bit node, the first pre-charge transistor to receive a clock signal via a first clock path; a second pre-charge transistor coupled to the bit bar node, the second pre-charge transistor to receive the clock signal via a second clock path; and control circuitry to; pass the clock signal to the first and second pre-charge transistors during a bit generation mode to generate a PUF bit at the bit node with a first value; and write a second value to the bit node during a delay hardening mode, the second value being a logical inverse of the first value. - View Dependent Claims (18, 19, 20, 21, 22, 23, 24)
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Specification