Temporal redundancy
First Claim
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1. A circuit for coupling to inter-chip communication channels, comprising:
- a first circuit to indicate whether at least one inter-chip communication channel is faulty;
a second circuit to distribute data bits associated with a faulty inter-chip communication channel to at least one non-faulty inter-chip communication channel; and
a third circuit to generate a clock signal that clocks transmission of data bits to the inter-chip communication channels, the clock signal being at an increased data rate when the first circuit indicates that at least one inter-chip communication channel is faulty,wherein the second circuit comprises a plurality of serializers having outputs coupled to the inter-chip communication channels and inputs coupled to a number of internal data channels, wherein each of the plurality of serializers is triggered by a respective control signal that determines which of the internal data channels is coupled to the input of the respective one of the plurality of serializers.
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Abstract
A circuit is provided to facilitate temporal redundancy for inter-chip communication. When an inter-chip communication channel fails, data bits associated with the faulty channel are steered to a non-faulty channel and transmitted via the non-faulty channel together with data bits associated with the non-faulty channel at an increased data rate.
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Citations
18 Claims
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1. A circuit for coupling to inter-chip communication channels, comprising:
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a first circuit to indicate whether at least one inter-chip communication channel is faulty; a second circuit to distribute data bits associated with a faulty inter-chip communication channel to at least one non-faulty inter-chip communication channel; and a third circuit to generate a clock signal that clocks transmission of data bits to the inter-chip communication channels, the clock signal being at an increased data rate when the first circuit indicates that at least one inter-chip communication channel is faulty, wherein the second circuit comprises a plurality of serializers having outputs coupled to the inter-chip communication channels and inputs coupled to a number of internal data channels, wherein each of the plurality of serializers is triggered by a respective control signal that determines which of the internal data channels is coupled to the input of the respective one of the plurality of serializers. - View Dependent Claims (2, 3, 4, 5, 6)
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7. A method, comprising:
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receiving a first signal indicating at least one inter-chip communication channel is faulty; and transmitting, by a plurality of serializers coupled to a number of internal data channels, data bits associated with a faulty inter-chip communication channel and data bits associated with a non-faulty inter-chip communication channel, via the non-faulty inter-chip communication channel, at an increased data rate; and triggering a respective one of the plurality of serializers with a control signal that determines which of the internal data channels is coupled to an input of the respective one of the plurality of serializers. - View Dependent Claims (8, 9, 10, 11, 12, 13, 14)
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15. A memory controller, comprising:
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a register to store information indicating a faulty inter-chip communication channel; a first circuit to re-associate data bits originally associated with the faulty inter-chip communication channel with one or more non-faulty inter-chip communication channels; and a second circuit to generate a clock signal to facilitate transmission or receiving of the re-associated data bits via one or more non-faulty inter-chip communication channels at an increased data rate, wherein the second circuit comprises a plurality of serializers having inputs coupled to a number of internal data channels, wherein each of the plurality of serializers is triggered by a respective control signal that determines which of the internal data channels is coupled to the input of the respective one of the plurality of serializers. - View Dependent Claims (16, 17, 18)
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Specification