System and method for routing-based internet security
First Claim
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1. An apparatus for connecting to a processor and to a location-addressable memory having an address space, the memory is connectable to the processor via a serial bus of a first type, the apparatus comprising:
- a first port couplable to a first serial bus of said first type for connecting to said processor;
a first interface coupled to said first port for receiving a first address word in said address space from said processor, the first address word consists of a sequence of bits, wherein each of the bits is associated with a level of significance;
a second port couplable to a second serial bus for connecting to said memory;
a second interface coupled to said second port for transmitting a second address word in said address space to said memory, the second address word consists of a sequence of bits, wherein each of the bits is associated with a level of significance;
a scrambler coupled between said first and second interfaces for converting using a one-to-one mapping said first address word to said second address word that is distinct from said first address word by re-arranging the sequence of at least two bits in said first address word;
a first serializer and first de-serializer coupled between said first interface and said scrambler, for converting to parallel the digital data received from said first interface and for serializing the digital data received from said scrambler; and
a second serializer and second de-serializer coupled between said second interface and said scrambler, for converting to parallel the digital data received from said second interface and for serializing the digital data received from said scrambler,wherein the converting comprises changing the significance level of at least two bits in said first address word.
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Abstract
Method and system for improving the security of storing digital data in a memory or its delivery as a message over the Internet from a sender to a receiver using one or more hops is disclosed. The message is split at the sender into multiple overlapping or non-overlapping slices according to a slicing scheme, and the slices are encapsulated in packets each destined to a different relay server as an intermediate node according to a delivery scheme. The relay servers relay the received slices to another other relay server or to the receiver. Upon receiving all the packets containing all the slices, the receiver combines the slices reversing the slicing scheme, whereby reconstructing the message sent.
345 Citations
97 Claims
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1. An apparatus for connecting to a processor and to a location-addressable memory having an address space, the memory is connectable to the processor via a serial bus of a first type, the apparatus comprising:
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a first port couplable to a first serial bus of said first type for connecting to said processor; a first interface coupled to said first port for receiving a first address word in said address space from said processor, the first address word consists of a sequence of bits, wherein each of the bits is associated with a level of significance; a second port couplable to a second serial bus for connecting to said memory; a second interface coupled to said second port for transmitting a second address word in said address space to said memory, the second address word consists of a sequence of bits, wherein each of the bits is associated with a level of significance; a scrambler coupled between said first and second interfaces for converting using a one-to-one mapping said first address word to said second address word that is distinct from said first address word by re-arranging the sequence of at least two bits in said first address word; a first serializer and first de-serializer coupled between said first interface and said scrambler, for converting to parallel the digital data received from said first interface and for serializing the digital data received from said scrambler; and a second serializer and second de-serializer coupled between said second interface and said scrambler, for converting to parallel the digital data received from said second interface and for serializing the digital data received from said scrambler, wherein the converting comprises changing the significance level of at least two bits in said first address word. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, 96, 97)
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Specification
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Current AssigneeMay Patents Ltd.
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Original AssigneeMay Patents Ltd.
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InventorsBinder, Yehuda
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Primary Examiner(s)SHOLEMAN, ABU S
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Application NumberUS14/492,551Publication NumberTime in Patent Office1,086 DaysField of Search713190, 709217US Class CurrentCPC Class CodesG06F 21/602 Providing cryptographic fac...G06F 21/78 to assure secure storage of...G06F 21/80 in storage media based on m...G06F 21/85 interconnection devices, e....G06F 7/58 Random or pseudo-random num...H04L 51/046 Interoperability with other...H04L 63/0281 ProxiesH04L 63/0428 wherein the data content is...H04L 63/18 using different networks or...H04L 67/63 Routing a service request d...
