Pixel array area optimization using stacking scheme for hybrid image sensor with minimal vertical interconnects

• US 9,763,566 B2
• Filed: 08/31/2015
• Issued: 09/19/2017
• Est. Priority Date: 05/12/2011
• Status: Active Grant

• Current Assignee: Depuy Synthes Products Incorporated (Johnson & Johnson)
• Original Assignee: Depuy Synthes Products Incorporated (Johnson & Johnson)
• Inventors: Blanquart, Laurent
• Primary Examiner(s): LUU, THANH X
• Application Number:
  US14/841,340
• Publication Number:
  US 20160190197A1
• Time in Patent Office: 750 Days
• Field of Search: 257686, 257777, 2502081
• CPC Class Codes: A61B 1/00009 of image signals during a use of endoscope
• CPC Class Codes: A61B 1/051 Details of CCD assembly
• CPC Class Codes: A61B 1/0676 at distal tip of an endoscope
• CPC Class Codes: H01L 24/17 of a plurality of bump connectors
• CPC Class Codes: H01L 24/20 Structure, shape, material or disposition of high density interconnect preforms
• CPC Class Codes: H01L 24/28 Structure, shape, material or disposition of the layer connectors prior to the connecting process
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 27/146 Imager structures
• CPC Class Codes: H01L 27/14601 Structural or functional details thereof
• CPC Class Codes: H01L 27/14603 Special geometry or disposition of pixel-elements, address-lines or gate-electrodes
• CPC Class Codes: H01L 27/14609 Pixel-elements with integrated switching, control, storage or amplification elements scanning details of imagers (circuitry of solid-state image sensors H04N25/00); circuitry of imagers H04N25/70
• CPC Class Codes: H01L 27/14618 Containers
• CPC Class Codes: H01L 27/14634 Assemblies, i.e. Hybrid structures
• CPC Class Codes: H01L 27/14636 Interconnect structures
• CPC Class Codes: H01L 27/14638 Structures specially adapted for transferring the charges across the imager perpendicular to the imaging plane
• CPC Class Codes: H01L 27/1464 Back illuminated imager structures
• CPC Class Codes: H01L 27/14641 Electronic components shared by two or more pixel-elements, e.g. one amplifier shared by two pixel elements
• CPC Class Codes: H01L 27/14643 Photodiode arrays; MOS imagers
• CPC Class Codes: H01L 27/14689 MOS based technologies
• CPC Class Codes: H01L 27/1469 : Assemblies, i.e. hybrid integration
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 : Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/381 : Pitch distance
• CPC Class Codes: H01L 31/028 : including, apart from doping material or other impurities, only elements of Group IV of the Periodic Table
• CPC Class Codes: H01L 31/0296 : including, apart from doping material or other impurities, only AIIBVI compounds, e.g. CdS, ZnS, HgCdTe
• CPC Class Codes: H01L 31/0304 : including, apart from doping materials or other impurities, only AIIIBV compounds
• CPC Class Codes: H04N 23/555 : for picking-up images in sites, inaccessible due to their dimensions or hazardous conditions, e.g. endoscopes or borescopes
• CPC Class Codes: H04N 23/56 : provided with illuminating means
• CPC Class Codes: H04N 25/75 : Circuitry for providing, modifying or processing image signals from the pixel array
• CPC Class Codes: H04N 25/767 : Horizontal readout lines, multiplexers or registers
• CPC Class Codes: H04N 25/772 : comprising A/D, V/T, V/F, I/T or I/F converters
• CPC Class Codes: H04N 25/778 : comprising amplifiers shared between a plurality of pixels, i.e. at least one part of the amplifier must be on the sensor array itself
• CPC Class Codes: H04N 25/78 : Readout circuits for addressed sensors, e.g. output amplifiers or A/D converters
• CPC Class Codes: H04N 25/79 : Arrangements of circuitry being divided between different or multiple substrates, chips or circuit boards, e.g. stacked image sensors

Abstract

Embodiments of a hybrid imaging sensor that optimizes a pixel array area on a substrate using a stacking scheme for placement of related circuitry with minimal vertical interconnects between stacked substrates and associated features are disclosed. Embodiments of maximized pixel array size/die size (area optimization) are disclosed, and an optimized imaging sensor providing improved image quality, improved functionality, and improved form factors for specific applications common to the industry of digital imaging are also disclosed.

Claims

1. An imaging sensor comprising:

a plurality of substrates comprising at least a first substrate and a second substrate;

a pixel array located on the first substrate and comprising a plurality of pixel columns;

a plurality of supporting circuits located on the second substrate and comprising a plurality of circuit columns, where one circuit column corresponds with one pixel column, wherein each of the plurality of circuit columns is defined as having an area that is substantially the same as and corresponds with an area of a corresponding pixel column;

a plurality of pixel column buses and a plurality of circuit column buses, wherein there is one pixel column bus per pixel column residing on the first substrate and one circuit column bus per circuit column residing on said second substrate; and

a plurality of interconnects, wherein at least one interconnect provides an electrical communication between one pixel column bus and one corresponding circuit column bus;

wherein at least a portion of each of the plurality of pixel column buses is superimposed with at least a portion of each of the corresponding plurality of circuit column buses, wherein said at least one interconnect is located anywhere along the superimposition of one pixel column bus and one corresponding circuit column bus.

2. The imaging sensor of claim 1, wherein the second substrate is disposed remotely relative to said first substrate;

wherein said plurality of supporting circuits are electrically connected to, and in electrical communication with, said pixel array; and

wherein said second substrate is disposed behind said pixel array relative to an object to be imaged.

3. The imaging sensor of claim 1, wherein each of the plurality of pixel columns comprises a plurality of detecting elements;

wherein the superimposition of each pixel column bus and each circuit column bus are such that the each pixel column bus and each corresponding circuit column bus are substantially aligned.

4. The imaging sensor of claim 1, wherein each of the plurality of pixel columns comprises an aspect ratio and each of the plurality of circuit columns comprises an aspect ratio;

wherein the aspect ratio of each of the plurality of pixel columns is the same and wherein the aspect ratio of each of the plurality of circuit columns is the same;

wherein the aspect ratio of each of the plurality of pixel columns comprises an area and wherein the aspect ratio of each of the plurality of circuit columns comprises an area, wherein the area of the plurality of pixel columns corresponds with the area of the plurality of circuit columns, and wherein the areas of the corresponding aspect ratios are substantially the same.

5. The imaging sensor of claim 1, wherein the electrical connection between one pixel column bus and one circuit column bus is accomplished by a single interconnect.

6. The imaging sensor of claim 1, wherein the electrical connection between one pixel column bus and one circuit column bus is accomplished by two interconnects.

7. The imaging sensor of claim 1, wherein said imaging sensor is backside illuminated.

8. The imaging sensor of claim 1, wherein said pixel array covers a substantial majority of a surface of said first substrate.

9. The imaging sensor of claim 1, wherein said pixel array covers more than twenty-five percent of a surface of said first substrate.

10. The imaging sensor of claim 1, wherein one of said supporting circuits is an analog to digital converter.

11. The imaging sensor of claim 1, wherein one of said supporting circuits is an amplifier circuit.

12. The imaging sensor of claim 1, wherein said second substrate is aligned with said first substrate in a stacked configuration.

13. The imaging sensor of claim 1, wherein said second substrate is disposed behind said first substrate and displaced laterally therefrom.

14. The imaging sensor of claim 1, wherein said first substrate is made of primarily silicon material.

15. The imaging sensor of claim 1, wherein said first substrate is made of primarily of “

High-Z”

semiconductor material, such as Cadmium Telluride.

16. The imaging sensor of claim 1, wherein said first substrate is made of III-V semiconductor materials.

17. The imaging sensor of claim 1, wherein the plurality of substrates further comprise a plurality of subsequent supporting substrates;

wherein said first substrate and said plurality of subsequent supporting substrates are stacked in alignment so that a plurality of communication columns are formed in a multi-layer stack.

18. An imaging sensor comprising:

a plurality of substrates comprising a first substrate and a second substrate;

a pixel array located on the first substrate comprising a plurality of pixel columns; and

a plurality of supporting circuits comprising a plurality of circuit columns located on the second substrate, wherein said plurality of supporting circuits are electrically connected to said pixel array;

a plurality of pixel column buses located on the first substrate and a plurality of circuit column buses located on the second substrate, wherein there is one pixel column bus per pixel column residing on the first substrate and one circuit column bus per circuit column residing on said second, subsequent supporting substrate;

wherein at least a portion of each of the plurality of pixel column buses is superimposed with at least a portion of each of the corresponding plurality of circuit column buses; and

wherein at least one interconnect electronically connects each of the pixel column buses to each of the corresponding circuit column buses.

19. The imaging sensor of claim 18, wherein the second substrate is disposed remotely relative to said first substrate;

wherein said plurality of supporting circuits are electrically connected to, and in electrical communication with, said pixel array; and

wherein said second substrate is disposed behind said pixel array relative to an object to be imaged.

20. The imaging sensor of claim 18, wherein each of the plurality of pixel columns comprises a plurality of detecting elements;

wherein the superimposition of each pixel column bus and each circuit column bus are such that the each pixel column bus and each corresponding circuit column bus are substantially aligned.

21. The imaging sensor of claim 18, wherein each of the plurality of pixel columns comprises an aspect ratio and each of the plurality of circuit columns comprises an aspect ratio;

wherein the aspect ratio of each of the plurality of pixel columns is the same and wherein the aspect ratio of each of the plurality of circuit columns is the same;

wherein the aspect ratio of each of the plurality of pixel columns comprises an area and wherein the aspect ratio of each of the plurality of circuit columns comprises an area, wherein the area of the plurality of pixel columns corresponds with the area of the plurality of circuit columns, and wherein the areas of the corresponding aspect ratios are substantially the same.

22. The imaging sensor of claim 18, wherein the electrical connection between one pixel column bus and one circuit column bus is accomplished by a single interconnect.

23. The imaging sensor of claim 18, wherein the electrical connection between one pixel column bus and one circuit column bus is accomplished by a two interconnects.

24. The imaging sensor of claim 18, wherein said imaging sensor is backside illuminated.

25. The imaging sensor of claim 18, wherein said pixel array covers a substantial majority of a surface of said first substrate.

26. The imaging sensor of claim 18, wherein said pixel array covers more than twenty-five percent of a surface of said first substrate.

27. The imaging sensor of claim 18, wherein one of said supporting circuits is an analog to digital converter.

28. The imaging sensor of claim 18, wherein one of said supporting circuits is an amplifier circuit.

29. The imaging sensor of claim 18, wherein said second substrate is aligned with said first substrate in a stacked configuration.

30. The imaging sensor of claim 18, wherein said second substrate is disposed behind said first substrate and displaced laterally therefrom.

31. The imaging sensor of claim 18, wherein said first substrate is made of primarily silicon material.

32. The imaging sensor of claim 18, wherein said first substrate is made of primarily of “

High-Z”

semiconductor material, such as Cadmium Telluride.

33. The imaging sensor of claim 18, wherein said first substrate is made of III-V semiconductor materials.

34. The imaging sensor of claim 18, wherein the plurality of substrates further comprise a plurality of subsequent supporting substrates;

wherein said first substrate and said plurality of subsequent supporting substrates are stacked in alignment so that a plurality of communication columns are formed in a multi-layer stack.