In-cell touch panel and display device

• US 9,766,761 B2
• Filed: 09/18/2014
• Issued: 09/19/2017
• Est. Priority Date: 05/30/2014
• Status: Active Grant

• Current Assignee: Beijing BOE Optoelectronics Technology Co Ltd. (BOE Technology Group Co., Ltd.), BOE Technology Group Co., Ltd.
• Original Assignee: Beijing BOE Optoelectronics Technology Co Ltd. (BOE Technology Group Co., Ltd.), BOE Technology Group Co., Ltd.
• Inventors: Wang, Lei, Xue, Hailin, Xue, Yanna, Liu, Hongjuan, Wang, Haisheng
• Primary Examiner(s): Bolotin, Dmitriy
• Application Number:
  US14/647,907
• Publication Number:
  US 20160246408A1
• Time in Patent Office: 1,097 Days
• Field of Search: 345173, 345174, 345 55, 345 90, 178 1803, 349 12, 445 24
• CPC Class Codes: G02F 1/13338 Input devices, e.g. touch panels
• CPC Class Codes: G02F 2201/121 common or background
• CPC Class Codes: G06F 3/0412 Digitisers structurally integrated in a display
• CPC Class Codes: G06F 3/04166 Details of scanning methods, e.g. sampling time, grouping of sub areas or time sharing with display driving Synchronisation with the driving of the display or the backlighting unit to avoid interferences generated internally G06F3/04184
• CPC Class Codes: G06F 3/0443 using a single layer of sensing electrodes

Abstract

An in-cell touch panel and a display device are disclosed. The in-cell touch panel includes a top substrate and a bottom substrate disposed oppositely to each other, a common electrode layer disposed on a side of the bottom substrate that faces the top substrate, and a touch sensing chip. The common electrode layer includes a plurality of independent self-capacitance electrodes. The touch sensing chip is configured to apply common electrode signals to self-capacitance electrodes in a display interval and determine touch positions by detecting capacitance value variation of self-capacitance electrodes in a touch interval. No additional process is added in the manufacturing process of the array substrate for the in-cell touch panel, thereby saving production costs and improving production efficiency.

Claims

1. An in-cell touch panel comprising a top substrate and a bottom substrate disposed oppositely to each other, a common electrode layer disposed on a side of the bottom substrate that faces the top substrate, a touch sensing chip, a plurality of wires configured for connecting self-capacitance electrodes to the touch sensing chip, and a plurality of metal wires disposed on a same layer as and insulated from the wires;

wherein,

the common electrode layer comprises a plurality of independent self-capacitance electrodes;

the touch sensing chip is configured to apply common electrode signals to self-capacitance electrodes in a display interval and determine a touch position by detecting capacitance value variation of self-capacitance electrodes in a touch interval; and

the metal wires and the wires are correspondingly in same straight lines and respectively connected in parallel with the self-capacitance electrodes overlapping with them.

2. The in-cell touch panel of claim 1, wherein the wires and the self-capacitance electrodes are disposed on different layers.

3. The in-cell touch panel of claim 2, further comprising:

a black matrix layer disposed on a side of the top substrate facing the bottom substrate or on a side of the bottom substrate facing the top substrate;

wherein

orthogonal projections of patterns of the wires on the bottom substrate are all within a region in which a pattern of the black matrix layer is located; and

orthogonal projections of gaps between adjacent two of the self-capacitance electrodes on the bottom substrate are all within the region in which the pattern of the black matrix layer is located.

4. The in-cell touch panel of claim 2, further comprising:

a pixel electrode layer disposed on a side of the bottom substrate that faces the top substrate and disposed on a different layer from the common electrode layer;

wherein,

a layer on which the wires are located is provided between the pixel electrode layer and the common electrode layer.

5. The in-cell touch panel of claim 2, further comprising:

gate signal lines and data signal lines intersecting each other and disposed on a side of the bottom substrate that faces the top substrate, wherein adjacent two gate signal line and adjacent two data signal line enclose a pixel; and

an extension direction of the wires is same as the gate signal lines or the data signal lines.

6. The in-cell touch panel of claim 5, wherein every two adjacent rows of pixels constitute a pixel group and two gate signal lines for providing gate scanning signals for these two rows of pixels are provided between these two rows of pixels;

and

the wires are disposed at gaps between adjacent pixel groups and on a same layer as the gate signal lines.

7. The in-cell touch panel of claim 5, wherein two gate signal lines are provided between adjacent rows of pixels;

and every two adjacent columns of pixels as one pixel group share one data signal line between these two columns of pixels; and

the wires are disposed at gaps between adjacent pixel groups and on a same layer as the data signal lines.

8. The in-cell touch panel of claim 1, further comprising:

a black matrix layer disposed on a side of the top substrate facing the bottom substrate or on a side of the bottom substrate facing the top substrate;

wherein

orthogonal projections of patterns of the wires on the bottom substrate are all within a region in which a pattern of the black matrix layer is located; and

orthogonal projections of gaps between adjacent two of the self-capacitance electrodes on the bottom substrate are all within the region in which the pattern of the black matrix layer is located.

9. The in-cell touch panel of claim 8, further comprising:

a pixel electrode layer disposed on a side of the bottom substrate that faces the top substrate and disposed on a different layer from the common electrode layer;

wherein,

a layer on which the wires are located is provided between the pixel electrode layer and the common electrode layer.

10. The in-cell touch panel of claim 8, further comprising:

gate signal lines and data signal lines intersecting each other and disposed on a side of the bottom substrate that faces the top substrate, wherein adjacent two gate signal line and adjacent two data signal line enclose a pixel; and

an extension direction of the wires is same as the gate signal lines or the data signal lines.

11. The in-cell touch panel of claim 10, wherein every two adjacent rows of pixels constitute a pixel group and two gate signal lines for providing gate scanning signals for these two rows of pixels are provided between these two rows of pixels;

and

the wires are disposed at gaps between adjacent pixel groups and on a same layer as the gate signal lines.

12. The in-cell touch panel of claim 10, wherein two gate signal lines are provided between adjacent rows of pixels;

and every two adjacent columns of pixels as one pixel group share one data signal line between these two columns of pixels; and

the wires are disposed at gaps between adjacent pixel groups and on a same layer as the data signal lines.

13. The in-cell touch panel of claim 1, further comprising:

a pixel electrode layer disposed on a side of the bottom substrate that faces the top substrate and disposed on a different layer from the common electrode layer;

wherein,

a layer on which the wires are located is provided between the pixel electrode layer and the common electrode layer.

14. The in-cell touch panel of claim 1, further comprising:

gate signal lines and data signal lines intersecting each other and disposed on a side of the bottom substrate that faces the top substrate, wherein adjacent two gate signal line and adjacent two data signal line enclose a pixel; and

an extension direction of the wires is same as the gate signal lines or the data signal lines.

15. The in-cell touch panel of claim 14, wherein every two adjacent rows of pixels constitute a pixel group and two gate signal lines for providing gate scanning signals for these two rows of pixels are provided between these two rows of pixels;

and

the wires are disposed at gaps between adjacent pixel groups and on a same layer as the gate signal lines.

16. The in-cell touch panel of claim 14, wherein two gate signal lines are provided between adjacent rows of pixels;

and every two adjacent columns of pixels as one pixel group share one data signal line between these two columns of pixels; and

the wires are disposed at gaps between adjacent pixel groups and on a same layer as the data signal lines.

17. A display device comprising the in-cell touch panel of claim 1.