Non-serialized push instruction for pushing a message payload from a sending thread to a receiving thread
First Claim
1. A processing unit for a data processing system including a co-processor including a switch, the processing unit comprising:
- a memory; and
a processor core coupled to the memory, wherein the processor core includes at least one execution unit that executes, in a sending thread, a first push instruction and a second push instruction subsequent to the first push instruction in a program order, wherein each of the first and second push instructions requests that a respective message payload be pushed to a mailbox of a receiving thread;
wherein the processor core, in response to executing the first and second push instructions, invokes calculation, by the switch, of an address of the mailbox and injection, by the switch, of the respective message payloads of the first and second push instructions into the mailbox, wherein the processor core invokes calculation of the address of the mailbox and injection of the message payloads into the mailbox by transmitting, to the switch, respective first and second co-processor requests to the switch via an interconnect fabric of the data processing system, wherein the processor core transmits the second co-processor request to the switch without regard to acceptance of the first co-processor request by the switch.
1 Assignment
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Accused Products
Abstract
In at least some embodiments, a processor core executes a sending thread including a first push instruction and a second push instruction subsequent to the first push instruction in a program order. Each of the first and second push instructions requests that a respective message payload be pushed to a mailbox of a receiving thread. In response to executing the first and second push instructions, the processor core transmits respective first and second co-processor requests to a switch in the data processing system via an interconnect fabric of the data processing system. The processor core transmits the second co-processor request to the switch without regard to acceptance of the first co-processor request by the switch.
32 Citations
14 Claims
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1. A processing unit for a data processing system including a co-processor including a switch, the processing unit comprising:
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a memory; and a processor core coupled to the memory, wherein the processor core includes at least one execution unit that executes, in a sending thread, a first push instruction and a second push instruction subsequent to the first push instruction in a program order, wherein each of the first and second push instructions requests that a respective message payload be pushed to a mailbox of a receiving thread; wherein the processor core, in response to executing the first and second push instructions, invokes calculation, by the switch, of an address of the mailbox and injection, by the switch, of the respective message payloads of the first and second push instructions into the mailbox, wherein the processor core invokes calculation of the address of the mailbox and injection of the message payloads into the mailbox by transmitting, to the switch, respective first and second co-processor requests to the switch via an interconnect fabric of the data processing system, wherein the processor core transmits the second co-processor request to the switch without regard to acceptance of the first co-processor request by the switch. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A data processing system including a switch, the data processing system comprising:
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a memory; an interconnect fabric; a processor core coupled to the memory and to the interconnect fabric, wherein the processor core includes at least one execution unit that executes, in a sending thread, a first push instruction and a second push instruction subsequent to the first push instruction in a program order, wherein each of the first and second push instructions requests that a respective message payload be pushed to a mailbox of a receiving thread, and wherein the processor core, in response to executing the first and second push instructions, invokes calculation, by the switch, of an address of the mailbox and injection, by the switch, of the respective message payloads of the first and second push instructions into the mailbox, wherein the processor core invokes calculation of the address of the mailbox and injection of the message payloads into the mailbox by transmitting, to the switch, respective first and second co-processor requests via the interconnect fabric; and a co-processor coupled to the interconnect fabric, wherein the co-processor includes the switch, and wherein the switch, responsive to acceptance of the first co-processor request, calculates the address of the mailbox and injects the respective message payload of the first co-processor request into the mailbox of the receiving thread, and, responsive to acceptance of the second co-processor request, injects the respective message payload of the second co-processor request into the mailbox of the receiving thread, wherein the processor core transmits the second co-processor request to the switch without regard to acceptance of the first co-processor request by the switch. - View Dependent Claims (9, 10, 11, 12, 13, 14)
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Specification