Task processor

• US 9,766,924 B2
• Filed: 07/06/2015
• Issued: 09/19/2017
• Est. Priority Date: 08/16/2007
• Status: Active Grant

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Renesas Electronics Corporation
• Inventors: Maruyama, Naotaka
• Primary Examiner(s): Coleman, Eric
• Application Number:
  US14/792,342
• Publication Number:
  US 20150301856A1
• Time in Patent Office: 806 Days
• Field of Search: None
• CPC Class Codes: G06F 9/461 Saving or restoring of program or task context
• CPC Class Codes: G06F 9/462 with multiple register sets
• CPC Class Codes: G06F 9/4812 by interrupt, e.g. masked
• CPC Class Codes: G06F 9/4843 by program, e.g. task dispatcher, supervisor, operating system
• CPC Class Codes: G06F 9/485 Task life-cycle, e.g. stopping, restarting, resuming execution G06F9/4881 takes precedence
• CPC Class Codes: G06F 9/50 Allocation of resources, e.g. of the central processing unit [CPU]

Abstract

A task processor includes a CPU, a save circuit, and a task control circuit. A task control circuit is provided with a task selection circuit and state storage units associated with respective tasks. When executing a predetermined system call instruction, the CPU notifies the task control circuit accordingly. When informed of the execution of a system call instruction, the task control circuit selects a task to be subsequently executed in accordance with an output from the selection circuit. When an interrupt circuit receives a high-speed interrupt request signal, the task switching circuit controls the state transition of a task by executing an interrupt handling instruction designated by the interrupt circuit.

Claims

1. A task control circuit comprising:

a state register that stores state data representing execution state of a task;

a task switching circuit that controls execution state of a task, wherein the task switching circuit, when a predetermined condition for interrupt is met, suspends operation of a processor, generates a save signal for instructing to save context information of a running task and sets state data of the running task from RUN state, indicating that the task is being executed, to another state.

2. The task control circuit according to claim 1, wherein, when the predetermined condition for interrupt is met, the task switching circuit generates the save signal and instructs to load context information of a task to be executed next.

3. The task control circuit according to claim 1, wherein the task switching circuit generates the save signal when a timeout occurs as the predetermined condition for interrupt.

4. The task control circuit according to claim 3, wherein, after a counter value is set upon transition of a task to WAIT state, the task switching circuit decrements the counter value periodically, and, when the counter value reaches a predetermined threshold value or below, the task switching circuit acknowledges a timeout and sets state data of the task from WAIT state to another state.

5. The task control circuit according to claim 1, wherein the task switching circuit generates the save signal upon receiving an interrupt request signal from an external source as the predetermined condition for interrupt.

6. The task control circuit according to claim 5, wherein the task switching circuit, upon receiving the interrupt request signal, sets state data of the running task from RUN state to another state and instructs execution of a task available for a purpose of processing the interrupt request signal.

7. A task control circuit connected to a processor that loads an instruction and an operand from a memory into a processing register and runs a task in accordance with the instruction and the operand in the processing register, the task control circuit comprising:

a state register that stores state data representing execution state of a task;

a task switching circuit that controls execution state of a task; and

an interrupt circuit, wherein, upon receiving an interrupt request signal from an external source, the task switching circuit suspends execution by the processor, and the interrupt circuit runs an interrupt process corresponding to the interrupt request signal.

8. The task control circuit according to claim 7, wherein the task switching circuit resumes execution by the processor upon completion of the interrupt process.

9. A task control circuit connected to a processor that loads an instruction and an operand from a memory into a processing register and runs a task by subjecting a plurality of instructions to a pipeline process in accordance with the instruction and the operand in the processing register, the task control circuit comprising:

a state register that stores state data representing execution state of a task; and

a task switching circuit that controls execution state of a task, wherein, when a predetermined condition for switching is met during the pipeline process, the task switching circuit sets state data of the task from RUN state, indicating that the task is being executed, to another state, interrupts the plurality of instructions in the pipeline process, and saves context information of the plurality of instructions occurring at a time of interruption in a predetermined storage area.

10. The task control circuit according to claim 9, wherein, when the predetermined condition for switching is met, the task switching circuit transmits to the processor an instruction signal for loading the context information of a task to be executed next from the predetermined storage area into the processing register.

11. The task control circuit according to claim 9, wherein, when the predetermined condition for switching is met, the task switching circuit interrupts the plurality of instructions without waiting for results of processing all of the plurality of instructions to be written back.

12. The task control circuit according to claim 9, wherein the task switching circuit resumes the task by resuming the pipeline process of the plurality of instructions of the task from the point of time of interruption.