Masking defective bits in a storage array

• US 9,766,972 B2
• Filed: 08/07/2014
• Issued: 09/19/2017
• Est. Priority Date: 08/07/2014
• Status: Active Grant

• Current Assignee: Pure Storage, Inc.
• Original Assignee: Pure Storage, Inc.
• Inventors: Davis, John D., Hayes, John, Tan, Zhangxi, Kannan, Hari, Miladinovic, Nenad
• Primary Examiner(s): Decady, Albert
• Assistant Examiner(s): DORMAN, CHRISTIAN M
• Application Number:
  US14/454,531
• Publication Number:
  US 20160041869A1
• Time in Patent Office: 1,139 Days
• Field of Search: 714773, 714763, 714 2, 714 3, 714 411, 714 43, 714 61, 714 613, 714 62, 714 621, 714 622, 714 624, 714 632
• CPC Class Codes: G06F 11/1008 in individual solid state devices G06F11/1004 takes precedence
• CPC Class Codes: G06F 11/1012 using codes or arrangements adapted for a specific type of error G06F11/1048 takes precedence
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 12/0646 Configuration or reconfiguration
• CPC Class Codes: G06F 12/08 in hierarchically structured memory systems, e.g. virtual memory systems
• CPC Class Codes: G11C 29/70 Masking faults in memories by using spares or by reconfiguring
• CPC Class Codes: G11C 29/76 using address translation or modifications
• CPC Class Codes: G11C 29/765 in solid state disks
• CPC Class Codes: G11C 29/88 with partially good memories
• CPC Class Codes: G11C 29/883 using a single defective memory device with reduced capacity, e.g. half capacity
• CPC Class Codes: G11C 29/886 combining plural defective memory devices to provide a contiguous address range, e.g. one device supplies working blocks to replace defective blocks in another device
• CPC Class Codes: H03M 13/05 using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits H03M13/2906 takes precedence
• CPC Class Codes: H03M 13/09 Error detection only, e.g. using cyclic redundancy check [CRC] codes or single parity bit
• CPC Class Codes: H03M 13/1102 Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
• CPC Class Codes: H03M 13/1515 Reed-Solomon codes
• CPC Class Codes: H03M 13/3761 using code combining, i.e. using combining of codeword portions which may have been transmitted separately, e.g. Digital Fountain codes, Raptor codes or Luby Transform [LT] codes

Abstract

A method of failure mapping is provided. The method includes distributing user data throughout a plurality of storage nodes through erasure coding, wherein the plurality of storage nodes are housed within a chassis that couples the storage nodes as a storage cluster. Each of the plurality of storage nodes has a non-volatile solid-state storage with flash memory or other types of non-volatile memory and the user data is accessible via the erasure coding from a remainder of the plurality of storage nodes in event of two of the plurality of storage nodes being unreachable. The method includes determining that a non-volatile memory block in the memory has a defect and generating a mask that indicates the non-volatile memory block and the defect. The method includes reading from the non-volatile memory block with application of the mask, wherein the reading and the application of the mask are performed by the non-volatile solid-state storage.

Claims

1. A method of failure mapping, comprising:

distributing user data throughout a plurality of storage nodes through erasure coding, wherein each of the plurality of storage nodes has a non-volatile solid-state storage with non-volatile memory;

determining that the non-volatile memory has a defect;

generating a mask that indicates the defect, the generating based on error correction of reads of the non-volatile solid-state storage, wherein the mask is one of a plurality of masks in a mask hierarchy in the storage cluster, wherein the mask hierarchy includes masks of differing physical levels of the non-volatile memory, and wherein the generating supports combining the masks of differing physical levels to generate one or more page specific masks; and

reading from the non-volatile memory with application of the mask, wherein the reading and the application of the mask are performed by the non-volatile solid-state storage.

2. The method of claim 1, wherein application of the mask comprises:

substituting of a replacement page for a defective page from the non-volatile memory.

3. The method of claim 1, wherein application of the mask comprises:

weighting a bit value corresponding to a stuck bit line, such that an error correction interprets the weighted bit value as a don'"'"'t care.

4. The method of claim 1, wherein application of the mask comprises:

assigning a log-likelihood-ratio (LLR) value of zero to a bit location corresponding to a stuck bit line, such that a decoding interprets the bit location as equally likely to be stuck at zero or one.

5. The method of claim 1, wherein application of the mask comprises:

combining a plurality of masks to form the mask, wherein the mask is specific to a page; and

masking at least one bit of the page, in accordance with the mask.

6. The method of claim 1, wherein application of the mask comprises:

replacing a first bit value corresponding to a faulty bit line, by a second bit value from a spare data area in the non-volatile memory.

7. The method of claim 1, wherein reading from the non-volatile memory, with application of the mask comprises:

reading one of a plurality of pages affected by a faulty bit line;

removing, from data produced by the reading, a first bit value corresponding to the faulty bit line;

inserting a second bit value, from a spare data area in the non-volatile memory, into a least significant bit (LSB) location or a most significant bit (MSB) location of the data produced by the reading; and

shifting a portion of the data produced by the reading so as to produce aligned data with the first bit value so removed and the second bit value so inserted.

8. The method of claim 1, wherein the determining comprises one of:

interpreting manufacturing information regarding the non-volatile memory;

characterizing the non-volatile memory, with a portion of the non-volatile memory assembled in each of the plurality of storage nodes;

or

analyzing diagnostic information produced during operation of the plurality of storage nodes.

9. A plurality of storage nodes in a chassis, comprising:

each of the plurality of storage nodes having a processor and a non-volatile solid-state storage having non-volatile memory for user data storage, each non-volatile solid-state storage having a controller;

the plurality of storage nodes configured to distribute the user data and metadata associated with the user data throughout the plurality of storage nodes;

the non-volatile solid-state storage configured to generate a plurality of masks in a mask hierarchy that includes masks of differing physical levels of the non-volatile memory, and supports combining the masks of differing physical levels to generate one or more page specific masks, such that each of the plurality of masks indicates the non-volatile memory has a defect;

the non-volatile solid-state storage configured to apply one of the plurality of masks in a read from the non-volatile memory; and

the non-volatile solid-state storage configured to produce data with one of a replacement bit value, a weighted value, or a don'"'"'t care bit value, substituting for a defective bit value as a result of applying the one of the plurality of masks in the read from the non-volatile memory.

10. The plurality of storage nodes in a chassis of claim 9, further comprising:

the plurality of storage nodes configured to determine that the non-volatile memory has a defective page or a faulty bit line across a block, die, or package, based on manufacturer information.

11. The plurality of storage nodes in a chassis of claim 9, further comprising:

the plurality of storage nodes configured to determine that the non-volatile memory of the non-volatile solid-state storage of one of the plurality of storage nodes has a defective page or a faulty bit line, based on error correction of reads of the non-volatile solid-state storage.

12. The plurality of storage nodes in a chassis of claim 9, further comprising:

the plurality of storage nodes configured to determine that the non-volatile memory of the non-volatile solid-state storage of one of the plurality of storage nodes has a defective page or a faulty bit line, based on diagnostic information produced by the plurality of storage nodes.

13. The plurality of storage nodes in a chassis of claim 9, wherein the replacement bit value is provided from a spare data area in the non-volatile memory.

14. The plurality of storage nodes in a chassis of claim 9, wherein the defective bit value is removed from a first location in the data and the replacement bit value is substituted in a second location in the data, with a portion of the data shifted to accommodate the replacement bit value.

15. A storage cluster, comprising:

a plurality of storage nodes, each of the plurality of storage nodes having a processor and non-volatile solid-state storage with non-volatile memory for storage of user data;

the plurality of storage nodes configured to distribute the user data and metadata associated with the user data throughout the plurality of storage nodes;

the non-volatile solid-state storage configured to determine that a portion of the non-volatile memory has a defect based on error correction of reads of the non-volatile solid-state storage;

the non-volatile solid-state storage configured to generate a mask that indicates the defect, and read from the non-volatile memory the portion having the defect with application of the mask; and

the non-volatile solid-state storage configured to generate further masks that indicate further defects of the non-volatile memory, wherein the mask and the further masks are in a mask hierarchy that includes masks of differing physical levels of the non-volatile memory, and supports combining the masks of differing physical levels to generate one or more page specific masks.

16. The storage cluster of claim 15, further comprising:

the non-volatile solid-state storage having an error correction block configured to interpret weights on bit locations in data resulting from the read from the non-volatile memory, wherein the mask is configured to indicate a faulty bit line by weighting a bit in the data resulting from the read from the non-volatile memory.

17. The storage cluster of claim 15, wherein:

the non-volatile memory includes a die that is known as defective at a time of assembly of the non-volatile memory;

the non-volatile solid-state storage is configured to receive manufacturer information regarding the die that is known defective; and

the non-volatile solid-state storage is configured to generate the mask based at least in part on the manufacturer information.

18. The storage cluster of claim 15, further comprising:

the non-volatile solid-state storage configured to store the mask as metadata in a memory coupled to the non-volatile solid-state storage.

19. The storage cluster of claim 15, further comprising:

the non-volatile solid-state storage configured to substitute a replacement page for a defective page.

20. The storage cluster of claim 15, further comprising:

the non-volatile solid-state storage configured to delete, in data from the read from the non-volatile memory, a first bit value resulting from a faulty bit line; and

the non-volatile solid-state storage configured to insert, into the data with the deleted first bit value, a second bit value from a spare data area in the non-volatile memory.