Memory device with volatile and non-volatile media

• US 9,767,017 B2
• Filed: 08/21/2014
• Issued: 09/19/2017
• Est. Priority Date: 12/13/2010
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Inventors: Talagala, Nisha, Flynn, David
• Primary Examiner(s): Bertram, Ryan
• Assistant Examiner(s): CHAN, TRACY C
• Application Number:
  US14/465,631
• Publication Number:
  US 20140365707A1
• Time in Patent Office: 1,125 Days
• Field of Search: 710308, 711103
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 12/0804 with main memory updating G06F12/0806 takes precedence
• CPC Class Codes: G06F 13/28 using burst mode transfer, e.g. direct memory access DMA, cycle steal G06F13/32 takes precedence
• CPC Class Codes: G06F 2212/202 Non-volatile memory
• CPC Class Codes: G06F 3/0619 in relation to data integrity, e.g. data losses, bit errors
• CPC Class Codes: G06F 3/0656 Data buffering arrangements
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]

Abstract

Apparatuses, systems, methods, and computer program products are disclosed for providing a memory device with volatile and non-volatile media. A volatile memory medium is on a circuit board configured to be installed on a memory bus of a processor. A non-volatile memory medium is on the same circuit board. A mapping module is configured to selectively store data in either the volatile memory medium or the non-volatile memory medium. The data is provided by way of one or more commands from the processor.

Claims

1. An apparatus comprising:

a client-addressable volatile memory medium on a circuit board, the circuit board configured to be installed on a memory bus of a processor;

a non-volatile memory medium on the same circuit board, the non-volatile memory medium accessible using a memory semantic interface and a block device interface; and

a mapping module configured to selectively store data in one of the volatile memory medium and the non-volatile memory medium, the data provided by way of one or more commands from the processor, wherein storing the data in the non-volatile memory medium using the memory semantic interface comprises storing the data in the client-addressable volatile memory medium and providing metadata to the client-addressable volatile memory medium, the metadata specifying an address of the non-volatile memory medium to which the data is stored in response to a predefined trigger.

2. The apparatus of claim 1, wherein the mapping module is configured to select one of the volatile memory medium and the non-volatile memory medium for storing the data based on an address associated with the data.

3. The apparatus of claim 1, wherein the mapping module is configured to select one of the volatile memory medium and the non-volatile memory medium for storing the data based on a flag included in the one or more commands from the processor.

4. The apparatus of claim 1, further comprising a request module configured to provide access to data of the non-volatile memory medium using memory semantic operations.

5. The apparatus of claim 4, wherein the memory semantic operations comprise one or more of a load memory operation and a store memory operation for the data of the non-volatile memory medium.

6. The apparatus of claim 1, wherein the mapping module comprises a hardware controller on the same circuit board as the volatile memory medium and the non-volatile memory medium.

7. The apparatus of claim 1, wherein the mapping module comprises computer executable code stored on a non-transitory computer readable medium, the computer executable code executable on the processor to selectively store the data in one of the volatile memory medium and the non-volatile memory medium.

8. The apparatus of claim 1, wherein the circuit board comprises a dual in-line memory module comprising the volatile memory medium and the non-volatile memory medium, the dual in-line memory module configured to be received by an adapter of a motherboard comprising the memory bus of the processor.

9. The apparatus of claim 1, wherein one or more of the volatile memory medium and the non-volatile memory medium is accessible over the memory bus using one or more of a double data rate (DDR) interface, a hypertransport interface, a quickpath interconnect interface, a direct memory access (DMA) interface, a remote DMA (RDMA) interface, and a third party DMA interface.

10. The apparatus of claim 1, wherein the data of the volatile memory medium is associated with an identifier of a persistent namespace, the persistent namespace configured to survive a restart event and to grant access to data of the identifier subsequent to the restart event.

11. The apparatus of claim 1, further comprising a secondary power source on the circuit board, wherein the volatile memory medium is within an isolation zone of the non-volatile memory medium and the isolation zone is configured to receive power from the secondary power source in response to the predefined trigger.

12. A system comprising:

a memory device in communication with a central processing unit (CPU);

a volatile memory of the memory device, the volatile memory mapped into an address space of the CPU; and

a non-volatile storage medium of the memory device, data of the non-volatile storage medium accessible to the CPU using an address space of the non-volatile storage medium, wherein the memory device provides access to the data of the non-volatile storage medium using a memory semantic interface over a memory bus of the CPU, and using a block device interface over the same memory bus of the CPU, wherein the memory device provides access to the data of the non-volatile storage medium using a memory semantic interface by storing the data in the volatile memory and providing metadata to the volatile memory, the metadata specifying an address of the non-volatile storage medium to which the data is stored in response to a predefined trigger.

13. The system of claim 12, wherein the address space of the non-volatile storage medium comprises a logical address space with logical addresses mapped to physical locations of the non-volatile storage medium.

14. The system of claim 12, further comprising the CPU, a motherboard, and a direct interface to the CPU, wherein the memory device is in communication with the CPU using the direct interface and the memory device is coupled to the motherboard.

15. The system of claim 14, wherein the direct interface comprises the memory bus of the CPU.

16. A method comprising:

receiving first and second requests from a processor over a direct connection with the processor to store data in a storage device in communication with the processor over the direct connection;

storing data of the first request in a client-addressable volatile memory of the storage device; and

storing data of the second request in a non-volatile memory of the storage device, the non-volatile memory accessible using a memory semantic interface and a block device interface, wherein storing the data in the non-volatile memory using the memory semantic interface comprises storing the data in the client-addressable volatile memory and providing metadata to the client-addressable volatile memory, the metadata specifying an address of the non-volatile memory to which the data is stored in response to a predefined trigger.

17. The method of claim 16, further comprising determining in which of the volatile memory and the non-volatile memory to store data of the first and second requests in response to receiving the first and second requests based on addresses of the data of the first and second requests.

18. The method of claim 16, wherein at least one of the first and second requests comprises a memory semantic store request.

19. The method of claim 16, wherein at least one of the first and second requests comprises a block storage write request.