Memory controller and memory system including the same

• US 9,767,053 B2
• Filed: 12/11/2013
• Issued: 09/19/2017
• Est. Priority Date: 12/11/2012
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Woo, Seonghoon, Kim, Haksun, Kwon, Euihyeok, Park, Jaegeun
• Primary Examiner(s): ABAD, FARLEY J
• Application Number:
  US14/102,979
• Publication Number:
  US 20140164673A1
• Time in Patent Office: 1,378 Days
• CPC Class Codes: G06F 13/1673 using buffers
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A memory controller connected with a storage medium via a plurality of channels is provided which includes a signal processing block including a plurality of signal processing engines; and a decoding scheduler configured to control a data path such that at least one activated signal processing engine of the plurality of signal processing engines is connected with the plurality of channels, respectively.

Claims

1. A memory controller which is connected with a storage medium via a plurality of channels, comprising:

a signal processing block including a plurality of signal processing engines;

a decoding scheduler configured to control a data path based on an operating condition of the memory controller, such that at least one activated signal processing engine of the plurality of signal processing engines is connected with the plurality of channels, respectively;

a plurality of first in first out buffers (FIFO)s configured to temporarily store data to be transferred to the plurality of channels; and

a first bus matrix configured to sequentially transfer first packet data, which includes data output from the plurality of FIFOs respectively, to the at least one activated signal processing engine based on control information included in the first packet data.

2. The memory controller of claim 1, further comprising:

a CPU configured to determine an operating condition of the memory controller; and

a register configured to store activation information of the plurality of signal processing engines, the memory controller being configured such that the activation information is decided according to a determination result of the CPU.

3. The memory controller of claim 2, wherein the memory controller is configured such that part or all of the plurality of signal processing engines is activated by the activation information stored at the register.

4. The memory controller of claim 1, further comprising:

an encoding scheduler configured to control a data path such that data in the plurality of FIFOs is transferred to the at least one activated signal processing engine from among the plurality of signal processing engines.

5. The memory controller of claim 4, wherein the encoding scheduler comprises:

a first packet generator configured to generate the first packet data by adding the control information to data output from each of the plurality of FIFOs based on a state of the at least one activated signal processing engine; and

the first bus matrix.

6. The memory controller of claim 5, wherein the decoding scheduler comprises:

a second packet generator configured to generate second packet data by adding control information to data output from each of the plurality of channels based on a state of the at least one activated signal processing engine; and

a second bus matrix configured to sequentially transfer the second packet data, which corresponds respectively to the plurality of channels, to the at least one activated signal processing engine based on the control information included in the second packet data.

7. The memory controller of claim 6, further comprising:

a CPU configured to determine an operating condition of the memory controller; and

a register configured to store activation information of the plurality of signal processing engines, the memory controller being configured such that the activation information is decided according to a determination result of the CPU,

wherein the memory controller is configured such that, if the determined operating condition of the memory controller is a high performance operating condition, the CPU decides a value of the register such that the plurality of signal processing engines are all activated.

8. The memory controller of claim 7, wherein the encoding scheduler is configured to generate the first packet data such that, when a signal processing engine from among the plurality of signal processing engines is performing an encoding operation, data is distributed to remaining signal processing engines from among activated ones of the plurality of signal processing engines other than the signal processing engine performing the encoding operation.

9. The memory controller of claim 7, wherein the decoding scheduler is configured to generate the second packet data such that, when a signal processing engine from among the plurality of signal processing engines is performing a decoding operation, data is distributed to remaining signal processing engines from among activated ones of the plurality of signal processing engines other than the signal processing engine performing the decoding operation.

10. The memory controller of claim 7, wherein the decoding scheduler is configured to generate the second packet data such that data transferred via one of the plurality of channels is distributed to activated ones of the plurality of signal processing engines.

11. The memory controller of claim 7, wherein the encoding scheduler is configured to generate the first packet data such that data transferred via one of the plurality of FIFOs is distributed to activated ones of the plurality of signal processing engines.

12. The memory controller of claim 7, wherein the plurality of signal processing engines are error correction code engines, compression engines, encryption engines, or hash key engines.

13. The memory controller of claim 1, wherein a total number of the plurality of signal processing engines is equal to or less than a total number of the plurality of channels.

14. The memory controller of claim 1, wherein each signal processing engine from among the plurality of signal processing engines is configured to operate according to a same error correction code algorithm.

15. A memory system comprising:

a storage medium; and

a memory controller connected with the storage medium via a plurality of channels,

wherein the memory controller includes,

a plurality of signal processing engines,

a plurality of first in first out buffers (FIFO)s configured to temporarily store data to be transferred to the plurality of channels,

an encoding/decoding block, and

a first bus matrix configured to sequentially transfer first packet data, which includes data output from the plurality of FIFOs respectively, to at least one activated signal processing engine, from among the plurality of signal processing engines, based on control information included in the first packet data,

the encoding/decoding block being configured to connect the plurality of signal processing engines to the plurality of channels respectively, when the memory system performs a memory operation that uses the plurality of channels.

16. The memory system of claim 15, wherein the memory controller comprises:

a CPU configured to generate a determination result by determining an operating condition of the memory controller;

a register configured to store activation information of the plurality of signal processing engines, the memory controller being configured to decide the activation information according to the determination result of the CPU; and

a decoding scheduler configured to control a data path such that the at least one activated signal processing engine is connected to the plurality of channels, respectively, the at least one activated signal processing engine being activated according to the activation information of the register,

the decoding scheduler being configured to control a data path such that data of the plurality of FIFOs is transferred to the at least one activated signal processing engine.

17. The memory system of claim 16, further comprising:

an encoding scheduler, the encoding scheduler including, a first packet generator configured to generate the first packet data by adding the control information to data output from each of the plurality of FIFOs based on a state of the at least one activated signal processing engine; and

the first bus matrix.

18. The memory system of claim 17, wherein the decoding scheduler comprises:

a second packet generator configured to generate second packet data by adding control information to data output from each of the plurality of channels based on a state of the at least one activated signal processing engine; and

a second bus matrix configured to sequentially transfer the second packet data, which corresponds respectively to the plurality of channels, to the at least one activated signal processing engine based on the control information included in the second packet data.

19. The memory system of claim 18, wherein the decoding scheduler is configured to generate packet data such that data transferred via one of the plurality of channels is distributed to activated ones of the plurality of signal processing engines.

20. The memory system of claim 18, wherein each signal processing engine from among the plurality of signal processing engines is an error correction code engine, compression engine, encryption engine, or hash key engine.

21. The memory system of claim 15, wherein the encoding/decoding block comprises:

a plurality of second signal processing engines, and the memory system is configured such that the plurality of second signal processing engines is activated to perform encoding and decoding operations when a use of the plurality of signal processing engines is stopped, activation of the plurality of second signal processing engines being decided according to an error rate.

22. A bandwidth controlling method of a memory controller which is connected with a storage medium via a plurality of channels, comprising:

receiving an input signal; and

processing the input signal with the memory controller using a signal processing level, the signal processing level of the input signal being determined according to an operating condition of the memory controller,

the memory controller including a plurality of signal processing engines, the plurality of signal processing engines including one or more activated signal processing engines and one or more signal processing engines that are not activated such that a total number of the one or more activated signal processing engines corresponds to the signal processing level, the processing of the input signal including,

generating packet data by adding control information to the input signal, the control information being based on states of the plurality of signal processing engines,

transferring the packet data to the one or more activated signal processing engines based on the control information included in the packet data, and

processing the packet data using the one or more activated signal processing engines,

each signal processing engine from among the plurality of signal processing engines being an error correction code engine, a compression engine, an encryption engine, or a hash key engine.

23. The bandwidth controlling method of claim 22, further comprising:

controlling a data path such that the one or more activated signal processing engines are connected to the plurality of channels, respectively.

24. The bandwidth controlling method of claim 22, further comprising:

controlling a data path such that the input signal is transferred to the one or more activated signal processing engines.

25. The bandwidth controlling method of claim 24, wherein the controlling a data path such that the processed signal is transferred to the one or more activated signal processing engines comprises:

generating packet data by adding control information to data output from the plurality of channels based on a state of the one or more activated signal processing engines; and

transferring signals corresponding to the plurality of channels to the one or more activated signal processing engines based on the control information included in the packet data.

26. A memory controller which is connected with a storage medium via a plurality of channels, comprising:

a signal processing block including a plurality of coding engines, the plurality of coding engines being configured to perform a signal processing operation;

a scheduler configured to cause a first plurality of data units to be sent to a selected number of the plurality of coding engines via the plurality of channels, the memory controller being configured to determine the selected number based on an operation mode of the memory controller;

a plurality of first in first out buffers (FIFO)s configured to temporarily store data to be transferred to the plurality of channels; and

a first bus matrix configured to sequentially transfer first packet data, which includes data output from the plurality of FIFOs respectively, to the selected number of the plurality of coding engines based on control information included in the first packet data,

the signal processing operation including one of a decoding operation and an encoding operation.

27. The memory controller of claim 26, wherein the scheduler is configured such that

for a first operation mode of the memory controller, the scheduler determines a first number as the selected number, and

for a second operation mode of the memory controller, the scheduler determines a second number as the selected number,

the first number being different from second number.