Filling vacant areas of an integrated circuit design

• US 9,767,242 B1
• Filed: 06/04/2013
• Issued: 09/19/2017
• Est. Priority Date: 03/18/2009
• Status: Active Grant

• Current Assignee: Pulsic Limited
• Original Assignee: Pulsic Limited
• Inventors: Balsdon, Graham
• Primary Examiner(s): Chiang, Jack
• Assistant Examiner(s): Bowers, Brandon
• Application Number:
  US13/909,872
• Time in Patent Office: 1,568 Days
• Field of Search: 716139
• CPC Class Codes: G06F 2119/18 Manufacturability analysis or optimisation for manufacturability
• CPC Class Codes: G06F 30/39 Circuit design at the physical level physical level design for reconfigurable circuits G06F30/347
• CPC Class Codes: G06F 30/392 Floor-planning or layout, e.g. partitioning or placement
• CPC Class Codes: G06F 30/394 Routing G06F30/396 takes precedence
• CPC Class Codes: Y02P 90/02 Total factory control, e.g. smart factories, flexible manufacturing systems [FMS] or integrated manufacturing systems [IMS]

Abstract

Vacant areas of a layer of an integrated circuit design are filled with shapes connected to the appropriate nets.

Claims

1. A method comprising:

using a computer, automatically creating a first shape comprising rectangles that is representative of free space on a first layer of an integrated circuit design;

automatically creating a second shape comprising rectangles that is representative of free space on a second layer of the integrated circuit design, wherein the second layer is different from the first layer;

automatically creating a first via shape in a third layer, different from the first and second layers, that overlaps both the first and second shapes;

determining whether the first shape is further coupled to a third shape on a fourth layer, different from the first and second layers, wherein the third shape is representative of a power voltage net;

if the first shape has a further coupling to the third shape, not discarding the first shape and the first via shape; and

forming an integrated circuit from the integrated circuit design.

2. The method of claim 1 comprising:

if the first shape does not have a further coupling to a third shape, discarding the first shape and the first via shape.

3. The method of claim 1 wherein a distance a leftmost edge of the first shape to a rightmost edge of the first shape does not exceed a maximum width specified for the automatic creation.

4. The method of claim 1 comprising:

upon request by a user, showing only the automatically generated shapes of the first layer on a display of the computer.

5. The method of claim 1 comprising:

determining whether the first shape is further coupled to a fourth shape on a fourth layer, different from the first and second layers, wherein the fourth shape is representative of a ground voltage net; and

if the first shape has a further coupling to a fourth shape, not discarding the first shape and the first via shape.

6. The method of claim 5 comprising:

if the first shape does not have a further coupling to a fourth shape, discarding the first shape and the first via shape.

7. The method of claim 1 comprising:

if the first shape does not have a further coupling to a third shape, discarding the first shape and the first via shape;

determining whether the first shape is further coupled to a fourth shape on a fourth layer, different from the first and second layers, wherein the fourth shape is representative of a ground voltage net;

if the first shape has a further coupling to a fourth shape, not discarding the first shape and the first via shape; and

if the first shape does not have a further coupling to a fourth shape, discarding the first shape and the first via shape.

8. The method of claim 1 wherein the automatically creating a first shape comprising rectangles that is representative of free space on a first layer of an integrated circuit design comprises:

determining where the first rectangle overlaps a previously drawn second rectangle on the first layer;

using at least one computer processor, oversizing the second rectangle to obtain a third rectangle;

using at least one computer processor, subtracting the third rectangle from the first rectangle to form a fourth rectangle, fifth rectangle, and sixth rectangle, wherein the fourth, fifth, and sixth rectangles each have a smaller area than the first rectangle and the fourth, fifth, and sixth rectangles overlap;

if the sixth rectangle has a smaller width than a first minimum width, discarding the sixth rectangle while keeping the fourth and fifth rectangles;

starting with an edge of the fourth rectangle, growing an island that extends from the edge to a limit line at a second minimum width; and

discarding portions of the fourth and fifth rectangles beyond the limit line to obtain a first shape comprising rectangles.

9. The method of claim 1 comprising:

determining whether the first shape is further coupled to a fourth shape on a fourth layer, different from the first and second layers, wherein the fourth shape is representative of a GND voltage net;

if the first shape has a further coupling to a fourth shape, not discarding the first shape and the first via shape;

providing a first target percentage and a second target percentage, wherein a sum of the first and second target percentages is less than or equal to 100, the first target percentage is representative of a percentage of rectangles in the first layer coupled to the power voltage net, and the second target percentage is representative of a percentage of rectangles in the first layer coupled to the ground voltage net; and

automatically coupling rectangles to the power or ground voltage nets according to the first target percentage and the second target percentage.

10. The method of claim 1 wherein when the first shape is coupled to the third shape, the first shape and the first via shape is not discarded, this results in the first shape being coupled to the second shape through the first via shape in the third layer, and the first shape being coupled to the power voltage net through the second and third shapes, thereby coupling free space on the first layer to the power voltage net.

11. The method of claim 1 comprising:

by way of not discarding the first shape and the first via shape, transforming free space on the first layer into the power voltage net.

12. The method of claim 1 comprising:

after the not discarding the first shape and the first via shape, denoting the first layer as being representative of the power voltage net.

13. The method of claim 1 wherein the creating a first shape comprising rectangles, transforms free space on the first layer into the first shape,

wherein the second shape comprising rectangles, transforms free space on the second layer into the second shape,

wherein the creating a first via shape in a third layer, different from the first and second layers, that overlaps both the first and second shapes, transforming the first layer and the second layer from being two different floating layers so the first layer and second layer are coupled together, and

wherein the determining whether the first shape is further coupled to a third shape on a fourth layer, different from the first and second layers, wherein the third shape is representative of a power voltage net, transforming the second layer from being a floating layer to being coupled to the power voltage net.

14. The method of claim 1 wherein the first layer and second layer third layer will be used to create a mask set for the fabrication of an integrated circuit.

15. The method of claim 1 wherein the automatically creating a first shape comprising rectangles that is representative of free space on a first layer of an integrated circuit design comprises:

determining where the first rectangle overlaps a previously drawn second rectangle on the first layer;

using at least one computer processor, oversizing the second rectangle to obtain a third rectangle;

using at least one computer processor, subtracting the third rectangle from the first rectangle to form a fourth rectangle, fifth rectangle, and sixth rectangle, wherein the fourth, fifth, and sixth rectangles each have a smaller area than the first rectangle and the fourth, fifth, and sixth rectangles overlap;

if the sixth rectangle has a smaller width than a first minimum width, discarding the sixth rectangle while keeping the fourth and fifth rectangles;

starting with an edge of the fourth rectangle, growing an island that extends from the edge to a limit line at a second minimum width;

discarding portions of the fourth and fifth rectangles beyond the limit line to obtain a first shape comprising rectangles;

determining whether the first shape is further coupled to a fourth shape on a fourth layer, different from the first and second layers, wherein the fourth shape is representative of a GND voltage net;

if the first shape has a further coupling to a fourth shape, not discarding the first shape and the first via shape;

providing a first target percentage and a second target percentage, wherein a sum of the first and second target percentages is less than or equal to 100, the first target percentage is representative of a percentage of rectangles in the first layer coupled to the power voltage net, and the second target percentage is representative of a percentage of rectangles in the first layer coupled to the ground voltage net; and

automatically coupling rectangles to the VCC or GND power or ground voltage nets according to the first target percentage and the second target percentage.

16. A system comprising:

a computer configured to

automatically create a first shape comprising rectangles that is representative of free space on a first layer of an integrated circuit design,

automatically create a second shape comprising rectangles that is representative of free space on a second layer of the integrated circuit design, wherein the second layer is different from the first layer,

automatically create a first via shape in a third layer, different from the first and second layers, that overlaps both the first and second shapes,

determine whether the first shape is further coupled to a third shape on the second layer, wherein the third shape is representative of a power voltage net,

and if the first shape has a further coupling to the third shape, not discard the first shape and the first via shape; and

at least one photolithography mask that is used for the fabrication of an integrated circuit, wherein the photolithography mask comprises at least one feature based on the third layer.

17. The system of claim 16 wherein the computer is configured to:

if the first shape does not have a further coupling to a third shape, discard the first shape and the via shape.

18. The system of claim 16 wherein the computer is configured to:

determine whether the first shape is further coupled to a fourth shape on the second layer, wherein the third shape is representative of a ground voltage net, and

if the first shape has a further coupling to a fourth shape, not discard the first shape and the via shape.

19. The system of claim 18 comprising:

if the first shape does not have a further coupling to a fourth shape, discarding the first shape and the via shape.

20. The system of claim 16 wherein the computer is configured to:

if the first shape does not have a further coupling to a third shape, discard the first shape and the first via shape,

determine whether the first shape is further coupled to a fourth shape on the second layer, wherein the third shape is representative of a ground voltage net,

if the first shape has further coupling to a fourth shape, not discard the first shape and the first via shape, and

if the first shape does not have a further coupling to a fourth shape, discard the first shape and the first via shape.

21. The system of claim 16 wherein the automatically create a first shape comprising rectangles that is representative of free space on a first layer of an integrated circuit design comprises:

determine where the first rectangle overlaps a previously drawn second rectangle on the first layer;

oversize the second rectangle to obtain a third rectangle;

subtract the third rectangle from the first rectangle to form a fourth rectangle, fifth rectangle, and sixth rectangle, wherein the fourth, fifth, and sixth rectangles each have a smaller area than the first rectangle and the fourth, fifth, and sixth rectangles overlap;

if the sixth rectangle has a smaller width than a first minimum width, discard the sixth rectangle while keeping the fourth and fifth rectangles;

starting with an edge of the fourth rectangle, grow an island that extends from the edge to a limit line at a second minimum width; and

discard portions of the fourth and fifth rectangles beyond the limit line to obtain a first shape comprising rectangles.

22. The system of claim 16 wherein the computer is configured to:

determine whether the first shape is further coupled to a fourth shape on the second layer, wherein the third shape is representative of a ground voltage net, and

if the first shape has a further coupling to a fourth shape, not discard the first shape and the via shape,

provide a first target percentage and a second target percentage, wherein a sum of the first and second target percentages is less than or equal to 100, the first target percentage is representative of a percentage of rectangles in the first layer coupled to the power voltage net, and the second target percentage is representative of a percentage of rectangles in the first layer coupled to the ground voltage net, and

automatically couple rectangles to the power or ground voltage nets according to the first target percentage and the second target percentage.

23. A method comprising:

using a computer, automatically creating a first shape comprising rectangles that is representative of free space on a first layer of an integrated circuit design;

automatically creating a second shape comprising rectangles that is representative of free space on a second layer of the integrated circuit design, wherein the second layer is different from the first layer;

automatically creating a first via shape in a third layer, different from the first and second layers, that overlaps both the first and second shapes;

when the first and second shapes do not overlap, finding a third shape on the second layer that was not automatically generated;

automatically creating a second via shape in the third layer that overlaps both the first and third shapes;

determining whether the first shape is further coupled to a third shape on a fourth layer, different from the first and second layers, wherein the third shape is representative of a power voltage net;

determining whether the first shape is further coupled to a fourth shape on the second layer, wherein the third shape is representative of a power voltage net;

if the first shape has a further coupling to a third or fourth shape, not discarding the first shape and the first via shape; and

forming an integrated circuit from the integrated circuit design.

24. The method of claim 23 comprising:

if the first shape does not have a further coupling to a third or fourth shape, discarding the first shape and the first via shape.

25. The method of claim 23 wherein the automatically creating a first shape comprising rectangles that is representative of free space on a first layer of an integrated circuit design comprises:

determining where the first rectangle overlaps a previously drawn second rectangle on the first layer;

using at least one computer processor, oversizing the second rectangle to obtain a third rectangle;

using at least one computer processor, subtracting the third rectangle from the first rectangle to form a fourth rectangle, fifth rectangle, and sixth rectangle, wherein the fourth, fifth, and sixth rectangles each have a smaller area than the first rectangle and the fourth, fifth, and sixth rectangles overlap;

if the sixth rectangle has a smaller width than a first minimum width, discarding the sixth rectangle while keeping the fourth and fifth rectangles;

starting with an edge of the fourth rectangle, growing an island that extends from the edge to a limit line at a second minimum width; and

discarding portions of the fourth and fifth rectangles beyond the limit line to obtain a first shape comprising rectangles.