Memory elements with dynamic pull-up weakening write assist circuitry

• US 9,767,892 B1
• Filed: 04/27/2016
• Issued: 09/19/2017
• Est. Priority Date: 04/27/2016
• Status: Active Grant

• Current Assignee: Tahoe Research Limited (f/k/a Learndale Limited) (Vector Capital Corporation)
• Original Assignee: Altera Corporation (Intel Corporation)
• Inventors: Kumar, Rajiv, Koay, Wei Yee
• Primary Examiner(s): TRAN, MICHAEL THANH
• Application Number:
  US15/140,188
• Time in Patent Office: 510 Days
• Field of Search: 365154, 365205
• CPC Class Codes: G11C 11/419 Read-write [R-W] circuits
• CPC Class Codes: G11C 5/148 Details of power up or power down circuits, standby circuits or recovery circuits
• CPC Class Codes: G11C 7/065 Differential amplifiers of latching type
• CPC Class Codes: G11C 7/1096 Write circuits, e.g. I/O line write drivers
• CPC Class Codes: G11C 7/227 Timing of memory operations based on dummy memory elements or replica circuits

Abstract

Integrated circuits with an array of memory cells are provided. Each memory cell may include at least one pair of cross-coupled inverters, write access transistors, and optionally a separate read port. The cross-coupled inverters in each memory cell may have a positive power supply terminal. The positive power supply terminal of each memory cell along a given column in the array may be coupled to a corresponding pull-up transistor. The pull-up transistor may receive a control signal from a pull-up weakening control circuit. The control signal may be temporarily elevated during write operations and may otherwise be driven back down to ground to help optimize read performance. The pull-up weakening control circuit may be implemented using a chain of n-channel transistors or a resistor chain.

Claims

1. An integrated circuit, comprising:

a pair of bit lines;

a column of memory cells coupled to the pair of bit lines, wherein each memory cell in the column of memory cells includes cross-coupled inverters with positive power supply terminals, and wherein the positive power supply terminals of each memory cell in the column of memory cells are coupled to only a first pull-up transistor having a gate terminal that receives an adjustable control signal; and

a pull-up weakening control circuit that outputs the adjustable control signal, the pull-up weakening control circuit drives the adjustable control signal to a ground power supply level during read operations and temporarily elevates the adjustable control signal above the ground power supply level during write operations.

2. The integrated circuit of claim 1, further comprising:

an additional pair of bit lines; and

an additional column of memory cells coupled to the additional pair of bit lines, wherein each memory cell in the additional column of memory cells includes cross-coupled inverters with positive power supply terminals, and wherein the positive power supply terminals of each memory cell in the additional column of memory cells are coupled to only a second pull-up transistor having a gate terminal that receives the adjustable control signal.

3. The integrated circuit of claim 1, further comprising:

a positive power supply line that is directly connected to the first pull-up transistor, wherein the first pull-up transistor comprises a p-channel transistor.

4. The integrated circuit of claim 1, wherein the pull-up weakening control circuit includes a chain of diode-connected n-channel transistors connected in series.

5. The integrated circuit of claim 4, wherein each diode-connected n-channel transistor in the chain has a gate terminal and a drain terminal that are shorted together.

6. The integrated circuit of claim 4, wherein the pull-up weakening control circuit further includes:

a first transistor with a drain terminal that is connected to only a first diode-connected n-channel transistor in the chain; and

a second transistor with a drain terminal that is connected to only a second diode-connected n-channel transistor in the chain that is different from the first diode-connected n-channel transistor.

7. The integrated circuit of claim 6, further comprising:

a first configuration memory element that provides a static control bit to a gate terminal of the first transistor; and

a second configuration memory element that provides a static control bit to a gate terminal of the second transistor.

8. The integrated circuit of claim 4, wherein the pull-up weakening control circuit includes a chain of resistors connected in series.

9. The integrated circuit of claim 8, wherein the pull-up weakening control circuit further includes:

a first transistor having a drain terminal that is connected to only a first intermediate node between first and second resistors in the chain and a source terminal; and

a second transistor having a drain terminal that is connected to only a second intermediate node between the second resistor and a third resistor in the chain and a source terminal that is shorted to the source terminal of the first transistor.

10. A method of operating an integrated circuit having a pull-up transistor that is shared among a column of memory cells, the method comprising:

with a pull-up weakening control circuit, outputting a control signal at a ground power supply voltage level to the pull-up transistor during read operations; and

with the pull-up weakening control circuit, temporarily adjusting the control signal to be different than the ground power supply voltage level during write operations.

11. The method of claim 10, further comprising:

generating a write track signal to control the pull-up weakening control circuit.

12. The method of claim 11, wherein generating the write track signal comprises using a flip-flop to generate the write track signal.

13. The method of claim 12, wherein using the flip-flop to generate the write track signal comprises using the flip-flop to receive a write enable signal, a clock signal, and a self-timed write done signal.

14. The method of claim 12, further comprising:

adjusting the control signal to a first predetermined voltage level during the write operations when the pull-up weakening control circuit is configured in a first state; and

adjusting the control signal to a second predetermined voltage level that is different than the first predetermined voltage level during the write operations when the pull-up weakening control is configured in a second state.

15. An integrated circuit, comprising:

a group of memory cells each of which includes inverting circuits having power supply terminals;

a single pull-up transistor that is coupled to the power supply terminals of the inverters in each memory cell in the group of memory cells, wherein the pull-up transistor is shared among the group of memory cells; and

a pull-up weakening control circuit that is configured to output a control signal at a first predetermined voltage level to the pull-up transistor in a first mode and that is configured to output the control signal at a second predetermined voltage level that is different than the first predetermined voltage level to the pull-up transistor in a second mode during write operations.

16. The integrated circuit of claim 15, further comprising:

an additional group of memory cells each of which includes inverting circuits having power supply terminals; and

another single pull-up transistor that is coupled to the power supply terminals of the inverters in each memory cell in the additional group of memory cells, wherein the another pull-up transistor is shared among the additional group of memory cells, and wherein the another pull-up transistor also receives the control signal generated by the pull-up weakening control circuit.

17. The integrated circuit of claim 15, wherein the pull-up weakening control circuit includes a chain of diode-connected n-channel transistors connected in series.

18. The integrated circuit of claim 15, wherein the pull-up weakening control circuit includes a chain of resistors connected in series.

19. The integrated circuit of claim 15, wherein the pull-up weakening control circuit comprises:

a first transistor with a source terminal;

a second transistor with a source terminal that is shorted to the source terminal of the first transistor;

a first memory element that provides a first control bit to the first transistor;

a second memory element that provides a second control bit to the second transistor, wherein only the first control bit is asserted in the first mode and wherein only the second control bit is asserted in the second mode;

a third transistor; and

a fourth transistor coupled in series with the third transistor between the source terminal of the first transistor and a ground line, wherein the third transistor receives a write track signal, and wherein the fourth transistor receives an inverted version of the write track signal.