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Memory elements with dynamic pull-up weakening write assist circuitry

  • US 9,767,892 B1
  • Filed: 04/27/2016
  • Issued: 09/19/2017
  • Est. Priority Date: 04/27/2016
  • Status: Active Grant
First Claim
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1. An integrated circuit, comprising:

  • a pair of bit lines;

    a column of memory cells coupled to the pair of bit lines, wherein each memory cell in the column of memory cells includes cross-coupled inverters with positive power supply terminals, and wherein the positive power supply terminals of each memory cell in the column of memory cells are coupled to only a first pull-up transistor having a gate terminal that receives an adjustable control signal; and

    a pull-up weakening control circuit that outputs the adjustable control signal, the pull-up weakening control circuit drives the adjustable control signal to a ground power supply level during read operations and temporarily elevates the adjustable control signal above the ground power supply level during write operations.

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