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Non-volatile composite nanoscopic fabric NAND memory arrays and methods of making same

  • US 9,767,902 B2
  • Filed: 03/14/2016
  • Issued: 09/19/2017
  • Est. Priority Date: 05/09/2005
  • Status: Active Grant
First Claim
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1. A non-volatile nanoscopic trace stack NAND memory array, comprising:

  • a plurality of word lines;

    a plurality of bit lines;

    a plurality of select lines;

    at least one reference line;

    a plurality of select field effect transistors (FETs), each select FET having a gate element in electrical communication with a select line, a first FET diffusion region in electrical communication with a bit line, and a second FET diffusion region; and

    a plurality of non-volatile memory cells, each non-volatile memory cell comprising;

    a field effect transistor (FET) having a gate element situated between two FET diffusion regions; and

    a region of a multi-layer nanoscopic trace stack having a first end and a second end, said multi-layer nanoscopic trace stack having a first layer comprised of a nanotube fabric and a second layer comprised of a matrix layer comprising a substantially homogeneous mixture of nanotubes and nanoscopic particles;

    wherein said first end of said region of said multi-layer nanoscopic trace stack is in electrical communication with a first FET diffusion region and said second end of said region of said multi-layer nanoscopic trace stack is in electrical communication with a second FET diffusion region;

    wherein said region of multi-layer nanoscopic trace stack forms a switching region between said first end and said second end with the distance between said first end and said second end defining a channel length of said switching region;

    wherein said gate element is in electrical communication with a word line;

    wherein adjacent non-volatile memory cells share a FET diffusion and an electrical connection between said FET diffusion and said multi-layer nanoscopic trace stack regions, forming interconnected strings of sub-arrays having a first end in electrical communication with said second diffusion region of a select FET and a second end in electrical communication with said at least one reference line.

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