Non-volatile composite nanoscopic fabric NAND memory arrays and methods of making same
First Claim
1. A non-volatile nanoscopic trace stack NAND memory array, comprising:
- a plurality of word lines;
a plurality of bit lines;
a plurality of select lines;
at least one reference line;
a plurality of select field effect transistors (FETs), each select FET having a gate element in electrical communication with a select line, a first FET diffusion region in electrical communication with a bit line, and a second FET diffusion region; and
a plurality of non-volatile memory cells, each non-volatile memory cell comprising;
a field effect transistor (FET) having a gate element situated between two FET diffusion regions; and
a region of a multi-layer nanoscopic trace stack having a first end and a second end, said multi-layer nanoscopic trace stack having a first layer comprised of a nanotube fabric and a second layer comprised of a matrix layer comprising a substantially homogeneous mixture of nanotubes and nanoscopic particles;
wherein said first end of said region of said multi-layer nanoscopic trace stack is in electrical communication with a first FET diffusion region and said second end of said region of said multi-layer nanoscopic trace stack is in electrical communication with a second FET diffusion region;
wherein said region of multi-layer nanoscopic trace stack forms a switching region between said first end and said second end with the distance between said first end and said second end defining a channel length of said switching region;
wherein said gate element is in electrical communication with a word line;
wherein adjacent non-volatile memory cells share a FET diffusion and an electrical connection between said FET diffusion and said multi-layer nanoscopic trace stack regions, forming interconnected strings of sub-arrays having a first end in electrical communication with said second diffusion region of a select FET and a second end in electrical communication with said at least one reference line.
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Abstract
A non-volatile nanotube switch and memory arrays constructed from these switches are disclosed. A non-volatile nanotube switch includes a conductive terminal and a nanoscopic element stack having a plurality of nanoscopic elements arranged in direct electrical contact, a first comprising a nanotube fabric and a second comprising a carbon material, a portion of the nanoscopic element stack in electrical contact with the conductive terminal. Control circuitry is provided in electrical communication with and for applying electrical stimulus to the conductive terminal and to at least a portion of the nanoscopic element stack. At least one of the nanoscopic elements is capable of switching among a plurality of electronic states in response to a corresponding electrical stimuli applied by the control circuitry to the conductive terminal and the portion of the nanoscopic element stack. For each electronic state, the nanoscopic element stack provides an electrical pathway of corresponding resistance.
90 Citations
22 Claims
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1. A non-volatile nanoscopic trace stack NAND memory array, comprising:
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a plurality of word lines; a plurality of bit lines; a plurality of select lines; at least one reference line; a plurality of select field effect transistors (FETs), each select FET having a gate element in electrical communication with a select line, a first FET diffusion region in electrical communication with a bit line, and a second FET diffusion region; and a plurality of non-volatile memory cells, each non-volatile memory cell comprising; a field effect transistor (FET) having a gate element situated between two FET diffusion regions; and a region of a multi-layer nanoscopic trace stack having a first end and a second end, said multi-layer nanoscopic trace stack having a first layer comprised of a nanotube fabric and a second layer comprised of a matrix layer comprising a substantially homogeneous mixture of nanotubes and nanoscopic particles; wherein said first end of said region of said multi-layer nanoscopic trace stack is in electrical communication with a first FET diffusion region and said second end of said region of said multi-layer nanoscopic trace stack is in electrical communication with a second FET diffusion region; wherein said region of multi-layer nanoscopic trace stack forms a switching region between said first end and said second end with the distance between said first end and said second end defining a channel length of said switching region; wherein said gate element is in electrical communication with a word line; wherein adjacent non-volatile memory cells share a FET diffusion and an electrical connection between said FET diffusion and said multi-layer nanoscopic trace stack regions, forming interconnected strings of sub-arrays having a first end in electrical communication with said second diffusion region of a select FET and a second end in electrical communication with said at least one reference line. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 13, 14, 15, 16, 17, 18, 19, 20)
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12. A non-volatile composite nanoscopic fabric NAND memory array, comprising:
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a plurality of word lines; a plurality of bit lines; a plurality of select lines; at least one reference line; a plurality of select field effect transistors (FETs), each select FET having a gate element in electrical communication with a select line, a first FET diffusion region in electrical communication with a bit line, and a second FET diffusion region; and a plurality of non-volatile memory cells, each non-volatile memory cell comprising; a field effect transistor (FET) having a gate element situated between two FET diffusion regions; and a region of a patterned composite nanoscopic fabric having a first end and a second end, said patterned composite nanoscopic fabric comprising a matrix layer comprising a substantially homogeneous mixture of nanotube elements and nanoscopic particles; wherein said first end of said region of patterned composite nanoscopic fabric is in electrical communication with a first FET diffusion region and said second end of said region of patterned composite nanoscopic fabric is in electrical communication with a second FET diffusion region; wherein said region of patterned composite nanoscopic fabric forms a switching region between said first end and said second end with the distance between said first end and said second end defining a channel length of said switching region; wherein said gate element is in electrical communication with a word line; wherein adjacent non-volatile memory cells share a FET diffusion and an electrical connection between said FET diffusion and said patterned composite nanoscopic fabric regions, forming interconnected strings of sub-arrays having a first end in electrical communication with said second diffusion region of a select FET and a second end in electrical communication with said at least one reference line. - View Dependent Claims (21, 22)
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Specification