Memory system performing read of nonvolatile semiconductor memory device

• US 9,767,913 B2
• Filed: 11/04/2016
• Issued: 09/19/2017
• Est. Priority Date: 11/06/2009
• Status: Active Grant

• Current Assignee: Kioxia Corporation
• Original Assignee: Toshiba Memory Corporation (Kioxia Corporation)
• Inventors: Nagashima, Hiroyuki
• Primary Examiner(s): Ho, Hoai V
• Application Number:
  US15/343,484
• Publication Number:
  US 20170053704A1
• Time in Patent Office: 319 Days
• Field of Search: 36518511
• CPC Class Codes: G06F 11/1048 using arrangements adapted for a specific error detection or correction feature
• CPC Class Codes: G06F 11/3466 Performance evaluation by tracing or monitoring
• CPC Class Codes: G06F 2201/88 Monitoring involving counting
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 11/5642 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/14 Circuits for erasing electrically, e.g. erase voltage switching circuits
• CPC Class Codes: G11C 16/24 Bit-line control circuits
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/34 Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
• CPC Class Codes: G11C 16/3418 Disturbance prevention or evaluation; Refreshing of disturbed memory data

Abstract

According to one embodiment, a memory system includes a nonvolatile semiconductor memory device, a voltage generation unit and a control unit. The nonvolatile semiconductor memory device includes a memory cell array having a plurality of blocks each including a plurality of memory cells, and a voltage generation unit configured to change a read level of the memory cell. The control unit controls write, read, and erase of the nonvolatile semiconductor memory device. The control unit changes the read level between a start of use of the nonvolatile semiconductor memory device and a timing after an elapse of a time.

Claims

1. A memory system comprising:

a nonvolatile semiconductor memory device including a memory cell array having a first block including a memory cell; and

a control unit configured to set a voltage supplied to the memory cell array in a read,

wherein

the control unit is configured to set a first voltage supplied to the memory cell of the first block in a first read in a first operation, and

the control unit is configured to set a second voltage supplied to the memory cell of the first block in a second read after a lapse of a first standing time from the first operation, the second voltage different from the first voltage.

2. The memory system of claim 1, wherein the second voltage is higher or lower than the first voltage.

3. The memory system of claim 1, wherein a time of the first read is different from a time of the second read.

4. The memory system of claim 3, wherein the time of the first read is different from the time of the second read by one of changing a precharge voltage of a sense node of the memory cell and changing the number of times of sense.

5. The memory system of claim 3, wherein a third voltage supplied to an unselected word line adjacent to a selected word line in the second read is higher than a fourth voltage supplied to the unselected word line in the first read.

6. The memory system of claim 1, wherein

the first read is performed after a first operation is performed m times (m is an integer of 1 or more), and

the second read is performed after the first operation is performed n times (n is an integer of m+1 or more).

7. The memory system of claim 1, wherein the control unit is configured to set the second voltage based on a standing time and an ambient temperature in the second read.

8. The memory system of claim 1, wherein in a case that a standing time is longer than a second time, the control unit is configured to set the second voltage lower than the first voltage.

9. The memory system of claim 1, wherein in a case that a standing time is equal or shorter than a second time, the control unit is configured to set the second voltage higher than the first voltage.

10. The memory system of claim 1, wherein in a case that an error is detected after the first read and the second read, the control unit is configured to perform a refresh operation.

11. A memory system comprising:

a nonvolatile semiconductor memory device including a memory cell array having a first block including a memory cell; and

a control unit configured to set a voltage supplied to the memory cell array in a read,

wherein

the control unit is configured to set a first voltage supplied to the memory cell of the first block in a first read after a first operation is performed m times (m is an integer of 1 or more), and

the control unit is configured to set a second voltage supplied to the memory cell of the first block in a second read after the first operation is performed n times (n is an integer of m+1 or more), the second voltage different from the first voltage, the second read performed after a lapse of a first standing time from the first read.

12. The memory system of claim 11, wherein the second voltage is higher or lower than the first voltage.

13. The memory system of claim 11, wherein a time of the first read is different from a time of the second read.

14. The memory system of claim 13, wherein the time of the first read is different from the time of the second read by one of changing a precharge voltage of a sense node of the memory cell and changing the number of times of sense.

15. The memory system of claim 13, wherein a third voltage supplied to an unselected word line adjacent to a selected word line in the second read is higher than a fourth voltage supplied to the unselected word line in the first read.

16. The memory system of claim 11, wherein the first operation is one of a write operation, a read operation, and an erase operation.

17. The memory system of claim 11, wherein the control unit is configured to set the second voltage based on a standing time and an ambient temperature in the second read.

18. The memory system of claim 11, wherein in a case that a standing time is longer than a second time, the control unit is configured to set the second voltage lower than the first voltage.

19. The memory system of claim 11, wherein in a case that a standing time is equal or shorter than a second time, the control unit is configured to set the second voltage higher than the first voltage.

20. The memory system of claim 11, wherein in a case that an error is detected after the first read and the second read, the control unit is configured to perform a refresh operation.

21. A memory system comprising:

a nonvolatile semiconductor memory device including a memory cell array having a first block including a memory cell; and

a control unit configured to set a voltage supplied to the memory cell array in a read,

wherein

the control unit is configured to set a first voltage supplied to the memory cell of the first block in a first read in a first operation, and

the control unit is configured to set a second voltage supplied to the memory cell of the first block in a second read after a lapse of a first standing time or more from the first operation, the second voltage different from the first voltage.