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Mitigation scheme for SRAM functionality

  • US 9,767,917 B2
  • Filed: 10/13/2015
  • Issued: 09/19/2017
  • Est. Priority Date: 10/13/2015
  • Status: Active Grant
First Claim
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1. A memory system comprising:

  • an array of memory cells, each memory cell comprising a programmable memory cell providing first true bit signal and complement bit signal outputs representing a stored bit value;

    a control circuit applying control signals for selecting a memory cell and controlling bit value write or read operations performed on the selected memory cell, said memory cell having an internal node providing one of the bit signal outputs;

    an edge detector circuit for detecting a strength of a signal transitioning in to or out from the selected memory cell by measuring a delay in a voltage signal transition at the internal node of the selected cell when writing a bit value signal to the selected memory cell, said edge detector circuit receiving said signal from the selected memory during said write operation, said edge detector circuit comprising a series of delay buffers and operatively connected latches, each latch for capturing an output of a delay buffer stage and configured to trigger upon detecting an associated delay of the voltage signal transition of said received signal;

    a variable voltage source for applying a supply voltage to said selected memory cell when performing a write or read operation, said supply voltage applied modifying the strength of said selected memory cell in accordance with said detected signal strength.

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