Mitigation scheme for SRAM functionality
First Claim
1. A memory system comprising:
- an array of memory cells, each memory cell comprising a programmable memory cell providing first true bit signal and complement bit signal outputs representing a stored bit value;
a control circuit applying control signals for selecting a memory cell and controlling bit value write or read operations performed on the selected memory cell, said memory cell having an internal node providing one of the bit signal outputs;
an edge detector circuit for detecting a strength of a signal transitioning in to or out from the selected memory cell by measuring a delay in a voltage signal transition at the internal node of the selected cell when writing a bit value signal to the selected memory cell, said edge detector circuit receiving said signal from the selected memory during said write operation, said edge detector circuit comprising a series of delay buffers and operatively connected latches, each latch for capturing an output of a delay buffer stage and configured to trigger upon detecting an associated delay of the voltage signal transition of said received signal;
a variable voltage source for applying a supply voltage to said selected memory cell when performing a write or read operation, said supply voltage applied modifying the strength of said selected memory cell in accordance with said detected signal strength.
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Accused Products
Abstract
An system and method are configured to degrade a memory cell PFET voltage based on a sensor reading of a current operating point. This will enable additional control over the SRAM device, particularly during a write operation. In one embodiment, a system of SRAM memory devices is configured as a smart sensor with real-time corrective circuit action. The system and method samples write and read timing operations and is adaptable by performing real-time corrective action. The degrading of PFET voltage to reduce it strength and improve write characteristics include an implementation that includes a charge pump controllable for altering by decreasing a voltage applied to the PFET of a selected memory cell. In a further embodiment, an edge detector is built into the circuit that real-time assesses the strength of the memory write operation. In a further implementation, control logic functions as a Finite State Machine.
20 Citations
16 Claims
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1. A memory system comprising:
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an array of memory cells, each memory cell comprising a programmable memory cell providing first true bit signal and complement bit signal outputs representing a stored bit value; a control circuit applying control signals for selecting a memory cell and controlling bit value write or read operations performed on the selected memory cell, said memory cell having an internal node providing one of the bit signal outputs; an edge detector circuit for detecting a strength of a signal transitioning in to or out from the selected memory cell by measuring a delay in a voltage signal transition at the internal node of the selected cell when writing a bit value signal to the selected memory cell, said edge detector circuit receiving said signal from the selected memory during said write operation, said edge detector circuit comprising a series of delay buffers and operatively connected latches, each latch for capturing an output of a delay buffer stage and configured to trigger upon detecting an associated delay of the voltage signal transition of said received signal; a variable voltage source for applying a supply voltage to said selected memory cell when performing a write or read operation, said supply voltage applied modifying the strength of said selected memory cell in accordance with said detected signal strength. - View Dependent Claims (2, 3, 4, 5)
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6. A method of operating a memory system having an array of memory cells, each memory cell comprising a programmable memory cell providing first true bit signal and complement bit signal outputs representing a stored bit value, the method comprising:
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applying control signals for selecting a memory cell and controlling a bit value write or read operation performed at the selected memory cell, said memory cell having an internal node providing one of the bit signal outputs; detecting a strength of a signal transitioning in to or out from the selected memory cell by measuring a delay in a voltage signal transition at the internal node of the selected cell when writing a bit value signal to the selected cell, wherein said measuring a delay in writing a bit value to the selected cell comprises; receiving, at an edge detector circuit, said signal from the selected memory during said write operation, said edge detector circuit comprising a series of delay buffers and operatively connected latches, each latch for capturing an output of a delay buffer stage; and triggering one of said latches upon detecting an associated delay of said voltage signal transition of said received signal; and applying, responsive to said detected strength, a supply voltage to said selected memory cell when performing a write or read operation, said supply voltage applied modifying the strength of said selected memory in accordance with said detected signal strength. - View Dependent Claims (7, 8)
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9. A method of operating a memory cell device of a memory system having an array of memory cells, each memory cell comprising a programmable memory cell providing first true bit signal and complement bit signal outputs representing a stored bit value, the method comprising:
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applying control signals to a memory cell of a first column for performing a write operation; applying control signals to the memory cell of said first column for reading said stored bit value; determining from said read value, a voltage delay associated with reading said bit value, wherein said determining from said read value a voltage delay associated with reading said bit value comprises; receiving, at an edge detector circuit, said signal from the selected memory cell during said read operation, said edge detector circuit comprising a series of delay buffers and operatively connected latches, each latch for capturing an output of a delay buffer stage, said method further comprising; triggering one of said latches upon detecting an associated delay of a voltage signal transition of said received signal; and using a triggered latch output signal to adjust a supply voltage applied to a memory cell, said triggered latch output signal selecting a supply voltage applied to a memory cell of a second column based on said voltage delay, said adjusted supply voltage at said applied memory cell improving a data write operation characteristic at the memory cell of the second column. - View Dependent Claims (10, 11, 12, 13)
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14. A memory system comprising:
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an array of memory cells, each memory cell comprising a programmable memory cell providing first true bit signal and complement bit signal outputs representing a stored bit value; a critical path monitor (CPM) element detecting one or more;
temperature shifts and voltage changes in said memory cells array, said detected temperature shifts and voltage changes causing an associated output voltage timing delay;an edge detector circuit for receiving a calibration signal based on a delay margin determined from an automatic built in self-test (ABIST) failure rate, said edge detector circuit comprising a series of delay buffers and operatively connected latches, each latch for capturing an output of a delay buffer stage and configured to trigger upon detecting an associated delay of a voltage signal transition of said received calibration signal; and a variable voltage source coupled to said CPM element for applying a supply voltage to said selected memory cell when performing a write or read operation, wherein a strength of the supply voltage applied to a selected memory cell is decreased in accordance with said associated voltage timing delay for a cell write operation. - View Dependent Claims (15, 16)
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Specification