Method of forming a semiconductor structure
First Claim
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1. A method of forming a semiconductor device, comprising:
- providing a substrate, wherein the substrate has a dielectric layer thereon, the dielectric layer has a gate trench therein and a gate dielectric layer is formed on a bottom of the gate trench;
sequentially forming a work function metal layer and a top barrier layer in the gate trench;
performing a treatment to the top barrier layer so as to form a silicon-containing top barrier layer; and
forming a low-resistivity metal layer in the gate trench,wherein the top barrier layer is a stacked structure comprising at least one N-rich TiN layer and at least one Ti-rich TiN layer, and an upmost layer of the stacked structure is a Ti-rich TiN layer.
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Abstract
A method of forming a semiconductor device is disclosed. A substrate having a dielectric layer thereon is provided. The dielectric layer has a gate trench therein and a gate dielectric layer is formed on a bottom of the gate trench. A work function metal layer and a top barrier layer are sequentially formed in the gate trench. A treatment is performed to the top barrier layer so as to form a silicon-containing top barrier layer. A low-resistivity metal layer is formed in the gate trench.
44 Citations
11 Claims
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1. A method of forming a semiconductor device, comprising:
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providing a substrate, wherein the substrate has a dielectric layer thereon, the dielectric layer has a gate trench therein and a gate dielectric layer is formed on a bottom of the gate trench; sequentially forming a work function metal layer and a top barrier layer in the gate trench; performing a treatment to the top barrier layer so as to form a silicon-containing top barrier layer; and forming a low-resistivity metal layer in the gate trench, wherein the top barrier layer is a stacked structure comprising at least one N-rich TiN layer and at least one Ti-rich TiN layer, and an upmost layer of the stacked structure is a Ti-rich TiN layer. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
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Specification