Mitigating electromigration effects using parallel pillars

• US 9,768,111 B2
• Filed: 12/03/2015
• Issued: 09/19/2017
• Est. Priority Date: 03/05/2013
• Status: Active Grant

• Current Assignee: Oracle International Corporation (Oracle Corporation)
• Original Assignee: Oracle International Corporation (Oracle Corporation)
• Inventors: O'Brien, Mark, Ballard, James G., Vedantam, Kiran, Nanua, Mini, Caruso, Salvatore
• Primary Examiner(s): Kik, Phallaka
• Application Number:
  US14/958,109
• Publication Number:
  US 20160086884A1
• Time in Patent Office: 656 Days
• Field of Search: 716130, 716129, 716119, 326101, 326102, 326103, 326 9, 326 31, 257387
• CPC Class Codes: G06F 2119/04 Ageing analysis or optimisation against ageing
• CPC Class Codes: G06F 2119/10 Noise analysis or noise optimisation
• CPC Class Codes: G06F 30/394 Routing G06F30/396 takes precedence
• CPC Class Codes: G06F 30/398 Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] optical proximity correction [OPC] design processes G03F1/36
• CPC Class Codes: H01L 23/522 including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
• CPC Class Codes: H01L 23/5225 Shielding layers formed together with wiring layers
• CPC Class Codes: H01L 23/5226 Via connections in a multilevel interconnection structure
• CPC Class Codes: H01L 23/528 Geometry or layout of the interconnection structure H01L27/0207 takes precedence; algorithms G06F30/00
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

Systems, methods, and other embodiments associated with an integrated circuit that includes a plurality of parallel pillar structures is described. In one embodiment, an integrated circuit includes a series of layers. The series of layers include a plurality of pillar metals in each of the series of layers. Pillars within each of the series of layers are oriented to be parallel. Pillars in adjacent layers are aligned to be perpendicular. Each of the plurality of pillar metals is a rectangular segment of metal. The plurality of pillar metals form a reconvergent mesh grid. The series of layers includes a plurality of vias connecting the plurality of parallel pillar metals between the series of layers. Vias of the plurality of vias are located at intersections in the reconvergent mesh grid.

Claims

1. An integrated circuit, comprising:

a series of layers comprising;

a plurality of pillar metals in each of the series of layers, wherein pillars within each of the series of layers are oriented to be parallel, wherein pillars in adjacent layers are aligned to be perpendicular, wherein each of the plurality of pillar metals is a rectangular segment of metal, and wherein the plurality of pillar metals form a reconvergent mesh grid; and

a plurality of vias connecting the plurality of parallel pillar metals between the series of layers, wherein vias of the plurality of vias are located at intersections in the reconvergent mesh grid.

2. The integrated circuit of claim 1, wherein a first layer in the series of layers is adjacent to a front end of line (FEOL) layer of the integrated circuit.

3. The integrated circuit of claim 1, wherein the series of layers are part of a back end of line (BEOL) portion of the integrated circuit.

4. The integrated circuit of claim 1, wherein pillars of the plurality of pillar metals in a first layer of the series of layers are connected to a driver pin.

5. The integrated circuit of claim 1, wherein a final layer in the series of layers connects with a structure in a package of the integrated circuit.

6. The integrated circuit of claim 1, wherein a width for each of the plurality of pillar metals is a function of a switching frequency of signals carried by the plurality of pillar metals, and wherein the plurality of pillar metals mitigate electromigration effects in the integrated circuit.

7. The integrated circuit of claim 1, wherein the plurality of pillar metals in each of the series of layers are spaced to be substantially symmetric, and wherein the plurality of pillar metals are located with a vertical rectangular column through the series of layers that comprises a footprint within the series of layers that is a subsection within a whole footprint of the series of layers.

8. A device, comprising:

a first plurality of metal bars arranged to be parallel within a first set of layers of a plurality of layers;

a second plurality of metal bars arranged to be parallel within a second set of layers of the plurality of layers and arranged to be perpendicular with the first plurality of metal bars;

a plurality of vias connecting the first plurality of metal bars and the second plurality of metal bars at points of overlap between adjacent layers of the plurality of layers,

wherein the first plurality of metal bars and the second plurality of metal bars are within a same rectangular footprint.

9. The device of claim 8, wherein the plurality of vias connect the first plurality of metal bars and the second plurality of metal bars to form an electrically connected grid of metal interconnects in the device.

10. The device of claim 9, wherein the grid connects a driver pin between the plurality of layers of the device with components of the device to provide electric signals to the components.

11. The device of claim 8, wherein successive layers of the plurality of layers include successively fewer metal bars than a number of metal bars in a first layer of the plurality of layers, and wherein the first layer of the plurality of layers is beneath a second layer and adjacent to a front end of line (FEOL) layer of the device.

12. The device of claim 8, wherein the first plurality of metal bars and the second plurality of metal bars are spaced substantially symmetrically within layers of the plurality of layers that are back end of line (BEOL) layers, and wherein one or more of the first or second plurality of metal bars are truncated to avoid additional structures routed through the plurality of layers.

13. The device of claim 8, wherein the first and the second plurality of metal bars are located within a vertical rectangular column through the plurality of layers that comprises a footprint within the plurality of layers that is a subsection within a whole footprint of the series of layers.

14. An integrated circuit, comprising:

a series of layers that are part of a back end of line (BEOL) portion of the integrated circuit, wherein a first layer is adjacent to a front end of line (FEOL) layer of the integrated circuit, and wherein a final layer in the series of layers connects a driver pin layer with a structure in a package of the integrated circuit;

a plurality of pillar metals in each of the series of layers, wherein pillars within each of the series of layers are oriented to be parallel, wherein pillars in adjacent layers are aligned to be perpendicular with pillars in adjoining layers, wherein each of the plurality of pillar metals is a rectangular segment of metal, and wherein the plurality of pillar metals form a reconvergent mesh grid; and

a plurality of vias connecting the plurality of parallel pillar metals between the series of layers, wherein vias of the plurality of vias are located at intersections in the reconvergent mesh grid.