Semiconductor package in package

• US 9,768,124 B2
• Filed: 09/11/2016
• Issued: 09/19/2017
• Est. Priority Date: 02/21/2007
• Status: Active Grant

• Current Assignee: Amkor Technology Singapore Holding Pte., Ltd. (Amkor Technology Incorporated)
• Original Assignee: Amkor Technology Incorporated
• Inventors: Scanlan, Christopher M., Berry, Christopher J.
• Primary Examiner(s): Graybill, David E
• Application Number:
  US15/261,965
• Publication Number:
  US 20160379933A1
• Time in Patent Office: 373 Days
• Field of Search: None
• CPC Class Codes: H01L 21/56 Encapsulations, e.g. encapsulation layers, coatings
• CPC Class Codes: H01L 21/561 Batch processing
• CPC Class Codes: H01L 21/568 Temporary substrate used as encapsulation process aid H01L21/4832 and H01L21/566 take precedence
• CPC Class Codes: H01L 2224/16227 the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2224/81 using a bump connector
• CPC Class Codes: H01L 2224/81005 being a temporary or sacrificial substrate
• CPC Class Codes: H01L 2224/81913 Plasma cleaning
• CPC Class Codes: H01L 2224/83 using a layer connector
• CPC Class Codes: H01L 2224/83005 being a temporary or sacrificial substrate
• CPC Class Codes: H01L 2224/85 using a wire connector
• CPC Class Codes: H01L 2224/85005 being a temporary or sacrificial substrate
• CPC Class Codes: H01L 2224/85913 Plasma cleaning
• CPC Class Codes: H01L 2224/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 23/3121 a substrate forming part of the encapsulation
• CPC Class Codes: H01L 23/3135 : Double encapsulation or coating and encapsulation
• CPC Class Codes: H01L 23/5385 : Assembly of a plurality of insulating substrates
• CPC Class Codes: H01L 23/5386 : Geometry or layout of the interconnection structure
• CPC Class Codes: H01L 23/5389 : the chips being integrally enclosed by the interconnect and support structures
• CPC Class Codes: H01L 23/552 : Protection against radiation, e.g. light or electromagnetic waves
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 24/32 : of an individual layer connector
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 24/81 : using a bump connector
• CPC Class Codes: H01L 24/83 : using a layer connector
• CPC Class Codes: H01L 24/85 : using a wire connector wire bonding in general B23K20/004
• CPC Class Codes: H01L 24/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 25/03 : all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
• CPC Class Codes: H01L 25/105 : the devices being of a type provided for in group H01L27/00
• CPC Class Codes: H01L 25/16 : the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15151 : the die mounting substrate comprising an aperture, e.g. for underfilling, outgassing, window type wire connections
• CPC Class Codes: H01L 2924/15313 : being a land array, e.g. LGA
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/19105 : in a side-by-side arrangement on a common die mounting substrate
• CPC Class Codes: H01L 2924/19107 : off-chip wires
• CPC Class Codes: H01L 2924/207 : Diameter ranges
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding
• CPC Class Codes: H05K 1/0216 : Reduction of cross-talk, noise or electromagnetic interference grounding H05K1/0215
• CPC Class Codes: H05K 1/181 : associated with surface mounted components

Abstract

A semiconductor package having a second semiconductor package or module integrated therein. The semiconductor package of the present invention typically comprises active and passive devices which are each electrically connected to an underlying substrate. The substrate is configured to place such active and passive devices into electrical communication with contacts of the substrate disposed on a surface thereof opposite that to which the active and passive devices are mounted. The module of the semiconductor package resides within a complimentary opening disposed within the substrate thereof. The module and the active and passive devices of the semiconductor package are each fully or at least partially covered by a package body of the semiconductor package.

Claims

1. A semiconductor package, comprising:

a substrate having an opening extending from a substrate top surface to a substrate bottom surface, wherein the substrate has a substrate conductive pattern disposed on the substrate top surface and a plurality of contacts disposed on the substrate bottom surface, the contacts being in electrical communication with the substrate conductive pattern;

an electronic component attached to the substrate top surface and electrically connected to the substrate conductive pattern;

an electronic module at least partially disposed within the opening and including a plurality of module contacts and a module body defining a side surface and a top surface of the electronic module, the electronic module further comprising;

a module substrate having a module conductive pattern disposed on a module substrate top surface, the module conductive pattern comprising a module conductive pattern top surface, the plurality of module contacts disposed on a module substrate bottom surface, the plurality module contacts being in electrical communication with the module conductive pattern, the module substrate further comprising a perimeter surface, wherein the module body extends to the perimeter surface such that no portion of the module conductive pattern top surface is exposed proximate to the perimeter surface; and

an electronic module component attached to the module substrate top surface and electrically connected to the module conductive pattern, wherein the module body encloses the electronic module component;

a package body at least partially enclosing the substrate, enclosing the electronic component, and enclosing the side surface and the top surface of the electronic module such that the contacts of the substrate and the module contacts of the electronic module are exposed in a common exterior surface of the semiconductor package; and

a shield structure at least laterally disposed between the electronic module component and the electronic component.

2. The semiconductor package of claim 1, wherein the package body physically contacts the shield structure.

3. The semiconductor package of claim 1, wherein the package body physically contacts top and side surfaces of the shield structure.

4. The semiconductor package of claim 1, wherein the shield structure is within a void disposed in the package body.

5. The semiconductor package of claim 4, wherein the void comprises a conical shape in cross-sectional view.

6. The semiconductor package of claim 1, wherein the shield structure is electrically coupled to the substrate conductive pattern.

7. The semiconductor package of claim 1, wherein the shield structure extends to overlie the top surface of the electronic module.

8. The semiconductor package of claim 1, wherein the module electronic component is disposed within the opening and disposed at least in part below the substrate top surface.

9. The semiconductor package of claim 1, wherein the module substrate top surface faces the substrate top surface.

10. The semiconductor package of claim 1 further in combination with a printed circuit board having a wiring pattern disposed thereon, the wiring pattern being configured to place the module contacts of the module into electrical communication with at least some of the contacts of the substrate when the contacts and the module contacts are each electrically connected to the wiring pattern.

11. A semiconductor package structure, comprising:

a substrate having an opening extending from a substrate top surface to a substrate bottom surface, wherein the substrate has a substrate conductive pattern disposed on the substrate top surface and a plurality of contacts disposed on the substrate bottom surface;

an electronic component electrically connected to the substrate conductive pattern;

an electronic module disposed within the opening and comprising a plurality of module contacts and a module body defining a side surface and a top surface of the electronic module, the electronic module further comprising;

a module substrate having a module conductive pattern disposed on a module substrate top surface, the module conductive pattern comprising a module conductive pattern top surface, the plurality of module contacts disposed on a module substrate bottom surface, the module substrate further comprising a perimeter surface, wherein the module body extends to the perimeter surface to cover the entirety of the module conductive pattern top surface proximate to the perimeter surface; and

an electronic module component electrically connected to the module conductive pattern, wherein the module body encloses the electronic module component;

a package body at least partially enclosing the substrate, enclosing the electronic component, and enclosing the side surface and the top surface of the electronic module such that the contacts of the substrate and the module contacts of the electronic module are exposed in a common exterior surface of the semiconductor package; and

a shield structure at least laterally disposed between the electronic module component and the electronic component.

12. The structure of claim 11, wherein the package body physically contacts the shield structure.

13. The structure of claim 11, wherein the package body physically contacts top and side surfaces of the shield structure.

14. The structure of claim 11, wherein the shield structure extends to overlap the top surface of the electronic module, and wherein the shield structure is electrically coupled to the substrate conductive pattern.

15. The structure of claim 11, wherein the module electronic component is disposed within the opening and at least partially disposed below the substrate top surface.

16. A semiconductor package structure, comprising:

a substrate having an opening extending from a substrate top surface to a substrate bottom surface, wherein the substrate has a substrate conductive pattern disposed on the substrate top surface and a plurality of contacts disposed on the substrate bottom surface;

an electronic component electrically connected to the substrate conductive pattern;

an electronic module disposed within the opening and including a plurality of module contacts and a module body defining a side surface and a top surface of the electronic module, the electronic module further comprising;

a module substrate having a module conductive pattern disposed on a module substrate top surface, the module conductive pattern comprising a module conductive pattern top surface, the plurality of module contacts disposed on a module substrate bottom surface, the module substrate further comprising a perimeter surface, wherein the module body extends to the perimeter surface such that the module conductive pattern top surface is completely covered proximate to the perimeter surface; and

an electronic module component electrically connected to the module conductive pattern, wherein the module body encloses the electronic module component;

a package body at least partially enclosing the substrate, enclosing the electronic component, and enclosing the side surface and the top surface of the electronic module such that the contacts of the substrate and the module contacts of the electronic module are exposed in a common exterior surface of the semiconductor package; and

a shield structure laterally disposed between the side surface of the electronic module and the electronic component.

17. The structure of claim 16, wherein the package body physically contacts the shield structure.

18. The structure of claim 16, wherein the package body physically contacts top and side surfaces of the shield structure.

19. The structure of claim 16, wherein the shield structure is further disposed to overlie the top surface of the electronic module, and wherein the shield structure is electrically coupled to the substrate conductive pattern.

20. The structure of claim 16, wherein the module electronic component is disposed within the opening and disposed below the substrate top surface.