Methods of forming multi-die package structures including redistribution layers

• US 9,768,145 B2
• Filed: 10/29/2015
• Issued: 09/19/2017
• Est. Priority Date: 08/31/2015
• Status: Active Grant

• Current Assignee: Parabellum Strategic Opportunities Fund LLC (Parabellum Capital LLC)
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Yu, Chen-Hua, Yee, Kuo-Chung, Wang, Tsung-Ding, Lee, Chien-Hsun
• Primary Examiner(s): Sandvik, Benjamin
• Assistant Examiner(s): RAMALLO, GUSTAVO G
• Application Number:
  US14/927,218
• Publication Number:
  US 20170062383A1
• Time in Patent Office: 691 Days
• CPC Class Codes: H01L 21/486 Via connections through the substrate with or without pins
• CPC Class Codes: H01L 21/563 Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
• CPC Class Codes: H01L 21/565 Moulds
• CPC Class Codes: H01L 21/568 Temporary substrate used as encapsulation process aid H01L21/4832 and H01L21/566 take precedence
• CPC Class Codes: H01L 21/76879 by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating plating on semiconductors in general H01L21/288
• CPC Class Codes: H01L 2224/02381 Side view
• CPC Class Codes: H01L 2224/04105 Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
• CPC Class Codes: H01L 2224/08137 the bodies being arranged next to each other, e.g. on a common substrate
• CPC Class Codes: H01L 2224/08146 the bonding area connecting to a via connection in the body
• CPC Class Codes: H01L 2224/12105 Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
• CPC Class Codes: H01L 2224/13147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2224/16227 the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/32245 the item being metallic
• CPC Class Codes: H01L 2224/73259 Bump and HDI connectors
• CPC Class Codes: H01L 2224/73267 Layer and HDI connectors
• CPC Class Codes: H01L 2224/81005 being a temporary or sacrificial substrate
• CPC Class Codes: H01L 2224/9222 Sequential connecting processes
• CPC Class Codes: H01L 2224/92224 the second connecting process involving a build-up interconnect
• CPC Class Codes: H01L 2225/06517 : Bump or bump-like direct electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06524 : Electrical connections formed on device or on substrate, e.g. a deposited or grown layer
• CPC Class Codes: H01L 2225/06527 : Special adaptation of electrical connections, e.g. rewiring, engineering changes, pressure contacts, layout
• CPC Class Codes: H01L 2225/06541 : Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
• CPC Class Codes: H01L 2225/06548 : Conductive via connections through the substrate, container, or encapsulation
• CPC Class Codes: H01L 2225/06589 : Thermal management, e.g. cooling
• CPC Class Codes: H01L 23/3114 : the device being a chip scale package, e.g. CSP
• CPC Class Codes: H01L 23/3128 : the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/367 : Cooling facilitated by shape of device H01L23/38, H01L23/40, H01L23/42, H01L23/44, H01L23/46 take precedence
• CPC Class Codes: H01L 23/3675 : characterised by the shape of the housing
• CPC Class Codes: H01L 23/49811 : Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads H01L23/49827 takes precedence
• CPC Class Codes: H01L 23/49816 : Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 23/49827 : Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 23/49838 : Geometry or layout
• CPC Class Codes: H01L 23/5226 : Via connections in a multilevel interconnection structure
• CPC Class Codes: H01L 23/5383 : Multilayer substrates H01L23/5385 takes precedence; multilayer metallisation on monolayer substrates H01L23/538
• CPC Class Codes: H01L 23/5385 : Assembly of a plurality of insulating substrates
• CPC Class Codes: H01L 23/5389 : the chips being integrally enclosed by the interconnect and support structures
• CPC Class Codes: H01L 24/03 : Manufacturing methods
• CPC Class Codes: H01L 24/09 : of a plurality of bonding areas
• CPC Class Codes: H01L 24/11 : Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/17 : of a plurality of bump connectors
• CPC Class Codes: H01L 24/19 : Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 24/20 : Structure, shape, material or disposition of high density interconnect preforms
• CPC Class Codes: H01L 25/0652 : the devices being arranged next and on each other, i.e. mixed assemblies
• CPC Class Codes: H01L 25/0655 : the devices being arranged next to each other
• CPC Class Codes: H01L 25/18 : the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/1432 : Central processing unit [CPU]
• CPC Class Codes: H01L 2924/1434 : Memory
• CPC Class Codes: H01L 2924/18161 : of a flip chip
• CPC Class Codes: H01L 2924/18162 : of a chip with build-up interconnect

Abstract

A semiconductor device and a method of making the same are provided. A first die and a second die are placed over a carrier substrate. A first molding material is formed adjacent to the first die and the second die. A first redistribution layer is formed overlying the first molding material. A through via is formed over the first redistribution layer. A package component is on the first redistribution layer next to the copper pillar. The package component includes a second redistribution layer. The package component is positioned so that it overlies both the first die and the second die in part. A second molding material is formed adjacent to the package component and the first copper pillar. A third redistribution layer is formed overlying the second molding material. The second redistribution layer is placed on a substrate and bonded to the substrate.

Claims

1. A method of making a semiconductor device, comprising:

placing a first die and a second die over a first substrate;

forming a first molding material adjacent to the first die and the second die;

forming a first redistribution layer electrically coupled to the first die and the second die and overlying the first molding material;

forming a first copper pillar coupled to and overlying the first redistribution layer;

placing a package component on the first redistribution layer next to the first copper pillar, the package component comprising a second redistribution layer, wherein the package component is positioned so that it overlies both the first die and the second die in part;

forming a second molding material adjacent to the package component and the first copper pillar;

forming a third redistribution layer electrically coupled to the package component and overlying the second molding material;

removing the first substrate; and

placing the third redistribution layer on a second substrate and bonding the third redistribution layer to the second substrate.

2. The method of claim 1, wherein the first die and the second die are central processing units.

3. The method of claim 1, wherein the package component comprises an interposer that comprises an integrated passive device.

4. The method of claim 1, further comprising placing a heat dissipation lid on the second substrate so that the first die, the second die, and the package component are disposed in an inner cavity of the heat dissipation lid.

5. The method of claim 1, wherein the package component comprises a third die, a fourth die, a fifth die, and a sixth die, the third die and the fourth die are positioned so they are beside each other, the fifth die and the sixth die are positioned so they are next to each other, and the third die and the fourth die overlie the fifth and sixth dies, wherein the third die and the fourth die are encased in a third molding material and the fifth die and the sixth die are encased in a fourth molding material.

6. The method of claim 1, further comprising:

placing a third die over the first substrate beside the first die, the third die comprising high bandwidth memory;

placing a fourth die over the first substrate beside the second die, the fourth die comprising high bandwidth memory; and

forming the first molding material adjacent to the third die and the fourth die;

wherein the first die and the second die are central processing units and the package component comprises high speed memory.

7. The method of claim 1, further comprising forming a second copper pillar and positioning the package component so that it is between the first and second copper pillar.

8. A method of forming a semiconductor device, comprising:

placing a first die and a second die side by side over a first substrate;

forming a first molding material adjacent to the first die and the second die;

forming a first redistribution layer electrically coupled to the first die and the second die and overlying the first molding material; and

placing a package comprising a third die, a fourth die, and a second redistribution layer over the first redistribution layer so that the package is positioned over the center point of a shortest distance between the first and second die, and a sidewall of the third die that is closest to a first edge of the first substrate and a sidewall of the fourth die that is closest to a second edge of the first substrate are offset from a closest sidewall of the first die and a closest sidewall of the second die.

9. The method of claim 8, further comprising:

bonding the package to a substrate on an opposite side of the package from the first redistribution layer;

wherein the first die and the second die are central processing units and the third die and the fourth die are memory.

10. The method of claim 8, further comprising:

forming a first through via coupled to and overlying the first redistribution layer;

forming a second molding material adjacent to the package and the first through via;

forming a third redistribution layer electrically coupled to the package and overlying the second molding material;

removing the first substrate; and

placing the third redistribution layer on a second substrate and bonding the third redistribution layer to the second substrate.

11. The method of claim 10, wherein the third die is positioned over the fourth die, and the third die is attached to the fourth die using wafer-to-wafer bonding.

12. The method of claim 10, wherein the third die and the fourth die are positioned beside each other and disposed over the second redistribution layer, a third redistribution layer overlies the third die and the fourth die, and a fifth die and a sixth die are disposed on and connected to the third redistribution layer.

13. The method of claim 12, wherein the third die and the fourth die are encased in a third molding material and the fifth die and the sixth die are encased in a fourth molding material.

14. The method of claim 13, wherein a second through via extends through the third molding material and a third through via extends through the fourth molding material.

15. A method, comprising:

placing a first die, a second die, and a third die on a first substrate;

forming a first redistribution layer over the first die, the second die, and the third die;

placing a first interposer and a second interposer over the first redistribution layer;

forming a second redistribution layer over the first interposer and the second interposer;

connecting the second redistribution layer to a second substrate; and

placing a heat dissipation lid over the second substrate, wherein the first die is disposed within an inner cavity of the heat dissipation lid.

16. The method according to claim 15, further comprising forming a plurality of through vias extending from the first redistribution layer to the second redistribution layer.

17. The method according to claim 15, wherein the first interposer overlies the first die and the second die, and the second interposer overlies the second die and the third die.

18. The method according to claim 17, wherein the second die is a logic die and the first die and the third die are memory dies.

19. The method according to claim 15, wherein each of the first interposer and the second interposer comprise an integrated passive device.

20. The method according to claim 15, further comprising:

forming a molding material extending along sidewalls of the first die, the second die, and the third die.