Methods, devices, and systems related to forming semiconductor power devices with a handle substrate

• US 9,768,271 B2
• Filed: 02/22/2013
• Issued: 09/19/2017
• Est. Priority Date: 02/22/2013
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Schubert, Martin F., Odnoblyudov, Vladimir, Basceri, Cem
• Primary Examiner(s): Huber, Robert
• Assistant Examiner(s): OAKLEY, JOHN-ROLF
• Application Number:
  US13/774,313
• Publication Number:
  US 20140239348A1
• Time in Patent Office: 1,670 Days
• Field of Search: 438458, 438739, 438751, 438167, 438172
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 21/6836 Wafer tapes, e.g. grinding or dicing support tapes adhesive tapes in general C09J7/20
• CPC Class Codes: H01L 2221/68327 used during dicing or grinding
• CPC Class Codes: H01L 2221/6834 used to protect an active side of a device or wafer
• CPC Class Codes: H01L 2221/68368 used in a transfer process involving at least two transfer steps, i.e. including an intermediate handle substrate
• CPC Class Codes: H01L 2221/68381 Details of chemical or physical process used for separating the auxiliary support from a device or wafer
• CPC Class Codes: H01L 27/0605 integrated circuits made of compound material, e.g. AIIIBV
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/0657 characterised by the shape of the body
• CPC Class Codes: H01L 29/1029 of field-effect transistors
• CPC Class Codes: H01L 29/2003 Nitride compounds
• CPC Class Codes: H01L 29/42316 for field-effect transistors
• CPC Class Codes: H01L 29/66462 with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
• CPC Class Codes: H01L 29/778 with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface H01L29/803 takes precedence
• CPC Class Codes: H01L 29/7787 with wide bandgap charge-carrier supplying layer, e.g. direct single heterostructure MODFET

Abstract

Methods of manufacturing device assemblies, as well as associated semiconductor assemblies, devices, systems are disclosed herein. In one embodiment, a method of forming a semiconductor device assembly includes forming a semiconductor device assembly that includes a handle substrate, a semiconductor structure having a first side and a second side opposite the first side, and an intermediary material between the semiconductor structure and the handle substrate. The method also includes removing material from the semiconductor structure to form an opening extending from the first side of the semiconductor structure to at least the intermediary material at the second side of the semiconductor structure. The method further includes removing at least a portion of the intermediary material through the opening in the semiconductor structure to undercut the second side of the semiconductor structure.

Claims

1. A method, comprising:

forming a semiconductor device assembly that includes;

a handle substrate;

a semiconductor structure having a first side, a second side opposite the first side, and a gate region, wherein the gate region is between the source and drain regions of a transistor device; and

an intermediary material between the semiconductor structure and the handle substrate;

removing material from the semiconductor structure to form an opening extending from the first side of the semiconductor structure to at least the intermediary material at the second side of the semiconductor structure, wherein the opening extends through the gate region; and

decoupling the semiconductor structure from the handle substrate, wherein decoupling the semiconductor structure includes;

attaching a transfer structure to the semiconductor structure at the first side and such that a portion of the transfer structure extends across, and thereby completely covers, the opening; and

removing at least a portion of the intermediary material via the opening in the gate region of the semiconductor structure to undercut the second side of the semiconductor structure, wherein removing the intermediary material includes exposing the intermediary material to an etchant via the opening and by flowing the etchant between the portion of the transfer structure and a portion of the handle substrate facing the portion of the transfer structure across the opening.

2. The method of claim 1 wherein:

the portion of the intermediary material is a first portion of the intermediary material;

the method further comprises forming a first trench proximate the source region, and a second trench proximate the drain region, wherein the first and second trenches extend from the first side of the semiconductor structure to at least the intermediary material at the second side of the semiconductor structure, and wherein the first and second trenches at least partially define a mesa in the semiconductor structure;

removing a second portion of the intermediary material via the first trench; and

removing a third portion of the intermediary via the second trench.

3. The method of claim 2 wherein:

the handle substrate comprises a poly-Aluminum Nitride substrate (p-AlN); and

the method comprises forming a power transistor that includes the mesa formed in the semiconductor structure.

4. The method of claim 2, further comprising removing material from the semiconductor structure to mechanically isolate active regions in the semiconductor structure.

5. The method of claim 2 wherein the opening in the gate region includes an elongated trench, and wherein the elongated trench and the first and second trenches are parallel to one another.

6. The method of claim 1 wherein exposing the intermediary material to the etchant further comprises etching the intermediary material to form a gap between the semiconductor structure and the handle substrate.

7. A method of forming a semiconductor device assembly, comprising:

forming a stack of semiconductor materials on a handle substrate, the stack of semiconductor materials including a gate region of a transistor device;

forming openings in the stack of semiconductor materials, wherein portions of the handle substrate are exposed through the openings, and wherein the openings include a first opening extending through the gate region, a second opening adjacent a source region of the transistor device, and a third opening adjacent a drain region of the transistor device;

attaching a transfer structure to the stack of semiconductor materials, wherein portions of the transfer structure extend across and completely cover corresponding ones of the openings to define passageways between the portions of the handle substrate and the corresponding portions of the transfer structure; and

undercutting the stack of semiconductor materials adjacent the openings in the stack of semiconductor materials, wherein undercutting the stack of semiconductor materials includes flowing etchant into the passageways.

8. The method of claim 7 wherein undercutting the stack of semiconductor materials further comprises at least partially submerging the stack of semiconductor materials in an etchant.

9. The method of claim 7, further comprising forming a semiconductor device, wherein the semiconductor device includes at least a portion of the stack of semiconductor materials.

10. The method of claim 9 wherein the transistor device is a power transistor.

11. The method of claim 9 wherein the transistor device is a high electron mobility transistor (HEMT) device.

12. The method of claim 9 wherein the semiconductor device is a direct-attach device.

13. The method of claim 7 wherein undercutting the portion of the stack of semiconductor materials comprises decoupling the stack of semiconductor materials from the handle substrate.

14. The method of claim 13, further comprising

forming a semiconductor device to include at least a portion of the stack of semiconductor materials;

forming a first electrical contact at a first side of the semiconductor device; and

forming a second electrical contact at a second side of the semiconductor device that is opposite the first side of the semiconductor device.

15. The method of claim 7, further comprising forming a semiconductor device to include at least a portion of the stack of semiconductor materials and a portion of the handle substrate.

16. The method of claim 7 wherein flowing the etchant includes submersing the handle substrate, the transfer structure, and the stack of semiconductor materials in the etchant.

17. The method of claim 7 wherein flowing the etchant includes decoupling the handle substrate from the stack of semiconductor materials with the transfer structure attached to the stack of semiconductor materials.