Short channel effect suppression

• US 9,768,301 B2
• Filed: 09/17/2015
• Issued: 09/19/2017
• Est. Priority Date: 12/23/2014
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Peng, Cheng-Yi, Ho, Chia-Cheng, Chang, Chih-Sheng, Yeo, Yee-Chia, Yang, Yu-Lin
• Primary Examiner(s): Campbell, Shaun
• Assistant Examiner(s): DEHNE, AARON A
• Application Number:
  US14/857,610
• Publication Number:
  US 20160181245A1
• Time in Patent Office: 733 Days
• CPC Class Codes: H01L 21/76224 using trench refilling with dielectric materials trench filling with polycristalline silicon H01L21/763; together with vertical isolation, e.g. trench refilling in a SOI substrate H01L21/76264
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823821 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823892 with a particular manufacturing method of the wells or tubs, e.g. twin tubs, high energy well implants, buried implanted layers for lateral isolation [BILLI]
• CPC Class Codes: H01L 27/0924 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/0638 for preventing surface leakage due to surface inversion layer, e.g. with channel stopper channel stoppers in combination with isolation region for integrated circuits H01L21/762
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/1054 with a variation of the composition, e.g. channel with strained layer for increasing the mobility
• CPC Class Codes: H01L 29/16 including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
• CPC Class Codes: H01L 29/161 including two or more of the elements provided for in group H01L29/16 , e.g. alloys H01L29/1604 takes precedence
• CPC Class Codes: H01L 29/66537 using a self aligned punch through stopper or threshold implant under the gate region H01L29/66606 takes precedence
• CPC Class Codes: H01L 29/66651 with a single crystalline channel formed on the silicon substrate after insulating device isolation
• CPC Class Codes: H01L 29/7849 the means being provided under the channel

Abstract

A semiconductor device includes a semiconductor substrate having a first region and a second region. The first region includes a first set of fin structures, the first set of fin structures comprising a first set of epitaxial anti-punch-through features of a first conductivity type. The first region further includes a first set of transistors formed over the first set of fin structures. The second region includes a second set of fin structures, the second set of fin structures comprising a second set of epitaxial anti-punch-through features of a second conductivity type opposite to the first conductivity type. The second region further includes a second set of transistors formed over the second set of fin structures. The first set of epitaxial anti-punch-through features and the second set of epitaxial anti-punch-through features are substantially co-planar.

Claims

1. A semiconductor device comprising:

a semiconductor substrate having a first region and a second region, both the first region and the second region comprising a plurality of isolation features;

the first region comprising;

a first set of fin structures separated by the isolation features, the first set of fin structures comprising a first set of epitaxial anti-punch-through features of a first conductivity type, wherein the first set of fin structures comprise a first set of epitaxial semiconductor layers disposed on the first set of epitaxial anti-punch-through features, the first set of epitaxial semiconductor layers being doped at a different doping concentration than the first set of epitaxial anti-punch-through features; and

a first set of transistors formed over the first set of fin structures; and

the second region comprising;

a second set of fin structures separated by the isolation features, the second set of fin structures comprising a second set of epitaxial anti-punch-through features of a second conductivity type opposite to the first conductivity type; and

a second set of transistors formed over the second set of fin structures;

wherein the first set of epitaxial anti-punch-through features and the second set of epitaxial anti-punch-through features are substantially co-planar, and wherein at least a portion of the first and second sets of epitaxial anti-punch-through features extend above top surfaces of the isolation features.

2. The semiconductor device of claim 1, wherein the first set of epitaxial anti-punch-through features comprises one of:

silicon germanium (SiGe) or Germanium (Ge).

3. The semiconductor device of claim 1, wherein the first set of epitaxial anti-punch-through features are doped with a p-type dopant.

4. The semiconductor device of claim 1, wherein the second set of epitaxial anti-punch-through features comprise one of:

Germanium (Ge) or a III-V semiconductor material.

5. The semiconductor device of claim 1, wherein the second set of epitaxial anti-punch-through features are doped with an n-type dopant.

6. The semiconductor device of claim 1, wherein the first set of epitaxial semiconductor layers comprises silicon (Si).

7. The semiconductor device of claim 1, wherein the second set of fin structures comprises a second set of epitaxial semiconductor layers disposed on the second set of epitaxial anti-punch-through features.

8. The semiconductor device of claim 7, wherein the second set of epitaxial semiconductor layers have a different doping concentration than the first set of epitaxial anti-punch-through features.

9. The semiconductor device of claim 7, wherein the second set of epitaxial semiconductor layers comprise silicon germanium (SiGe).

10. The semiconductor device of claim 1, wherein the first set of epitaxial anti-punch-through features have a different lattice constant than the first set of epitaxial semiconductor layers and the second set of epitaxial anti-punch-through features have a different lattice constant than the second set of semiconductor layers.

11. The semiconductor device of claim 1, wherein the first set of epitaxial anti-punch-through features are differently stressed than the first set of epitaxial semiconductor layers and the second set of epitaxial anti-punch-through features are differently stressed than the second set of epitaxial semiconductor layers.

12. The semiconductor device of claim 1, wherein the first set of epitaxial anti-punch-through features comprise a different semiconductor material than the first set of epitaxial semiconductor layers and the second set of epitaxial anti-punch-through features comprise a different semiconductor material than the second set of epitaxial semiconductor layers.

13. A method comprising:

providing a substrate having a first region and a second region;

epitaxially forming a first anti-punch-through layer in the first region of the substrate with in-situ doping of a first conductivity type;

epitaxially forming a first semiconductor layer over the first anti-punch-through layer in the first region;

after forming the first semiconductor layer, epitaxially forming a second anti-punch-through layer in the second region of the substrate with in-situ doping of a second conductivity type, the second anti-punch-through layer being formed co-planar with the first anti-punch-through layer, the second conductivity type being opposite of the first conductivity type;

epitaxially forming a second semiconductor layer over the second anti-punch-through layer in the second region, the second semiconductor layer being formed co-planar with the first semiconductor layer;

after forming the second semiconductor layer, forming a plurality of isolation features within the substrate;

removing an upper portion of the isolated features to form a first set of fin structures in the first region and a second set of fin structures in the second region such that at least a portion of the first and second anti-punch-through layers are exposed.

14. The method of claim 13, further comprising, forming transistors on the first set of fin structures and the second set of fin structures.

15. The method of claim 13, wherein the forming a plurality of isolation features within the substrate includes:

performing a process to form trenches through the first anti-punch-through layer and the first semiconductor layer and forming second trenches through the second anti-punch-through layer and the second semiconductor layer;

filling in a dielectric material in the trenches; and

performing a planarizing process to the dielectric material.

16. A semiconductor device comprising:

an n-type region comprising;

a first set of fin structures separated by a first set of isolation features, the fin structures of the first set varying in size, the fin structures of the first set comprising a first set of epitaxial anti-punch-through features positioned at varying depths, wherein the first set of fin structures comprise a first set of epitaxial semiconductor layers disposed on the first set of epitaxial anti-punch-through features, the first set of epitaxial semiconductor layers being doped at a different doping concentration than the first set of epitaxial anti-punch-through features; and

a plurality of n-type transistors formed on the fin structures of the first set; and

a p-type region comprising;

a second set of fin structures separated by a second set of isolation features, the fin structures of the second set varying in size, the fin structures of the second set comprising a second set of epitaxial anti-punch-through features at varying depths; and

a plurality of p-type transistors formed on the fin structures of the second set;

wherein at least a portion of the first and second sets of epitaxial anti-punch-through features extend above top surfaces of the first and second sets of epitaxial anti-punch-through features.

17. The semiconductor device of claim 16, wherein the first set of epitaxial anti-punch-through features are doped with a p-type dopant.

18. The semiconductor device of claim 16, wherein the second set of epitaxial anti-punch-through features are doped with an n-type dopant.

19. The semiconductor device of claim 16, wherein the second set of fin structures comprise a second set of epitaxial semiconductor layers disposed on the second set of epitaxial anti-punch-through features.

20. The semiconductor device of claim 19, wherein the second set of epitaxial semiconductor layers are doped at a different doping concentration than the second set of epitaxial anti-punch-through features.