Semiconductor device and method for manufacturing the same

• US 9,768,307 B2
• Filed: 12/27/2016
• Issued: 09/19/2017
• Est. Priority Date: 06/17/2011
• Status: Expired due to Fees

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Yamazaki, Shunpei, Honda, Tatsuya
• Primary Examiner(s): MENZ, LAURA MARY
• Application Number:
  US15/391,027
• Publication Number:
  US 20170110590A1
• Time in Patent Office: 266 Days
• CPC Class Codes: H01L 21/02554 Oxides
• CPC Class Codes: H01L 21/02565 Oxide semiconducting materials not being Group 12/16 materials, e.g. ternary compounds
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 27/14616 characterised by the channel of the transistor, e.g. channel having a doping gradient
• CPC Class Codes: H01L 29/045 by their particular orientation of crystalline planes
• CPC Class Codes: H01L 29/66969 of devices having semiconductor bodies not comprising group 14 or group 13/15 materials comprising selenium or tellurium in uncombined form other than as impurities in semiconductor bodies of other materials, comprising cuprous oxide or cuprous iodide H01L21/02365
• CPC Class Codes: H01L 29/78609 for preventing leakage current H01L29/78618 takes precedence
• CPC Class Codes: H01L 29/78621 with LDD structure or an extension or an offset region or characterised by the doping profile
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

An object is to provide a structure of a transistor which has a channel formation region formed using an oxide semiconductor and a positive threshold voltage value, which enables a so-called normally-on switching element. The transistor includes an oxide semiconductor stack in which at least a first oxide semiconductor layer and a second oxide semiconductor layer with different energy gaps are stacked and a region containing oxygen in excess of its stoichiometric composition ratio is provided.

Claims

1. A method for manufacturing a semiconductor device, comprising the steps of:

forming an oxide semiconductor stack including a first oxide semiconductor layer and a second oxide semiconductor layer with an energy gap different from an energy gap of the first oxide semiconductor layer;

forming a source electrode layer and a drain electrode layer over the oxide semiconductor stack;

forming a gate insulating film over the source electrode layer and the drain electrode layer;

introducing oxygen into the oxide semiconductor stack with use of the source electrode layer and the drain electrode layer as a mask; and

forming a gate electrode layer overlapping the oxide semiconductor stack with the gate insulating film interposed therebetween.

2. The method for manufacturing a semiconductor device according to claim 1, further comprising a step of introducing dopant into the oxide semiconductor stack with use of the gate electrode layer as a mask.

3. The method for manufacturing a semiconductor device according to claim 1, further comprising steps of:

forming an interlayer insulating film over the gate electrode layer;

forming a contact hole in the interlayer insulating film so as to reach at least one of the source electrode layer and the drain electrode layer; and

forming a wiring layer over the interlayer insulating film, wherein the wiring layer is connected to the at least one of the source electrode layer and the drain electrode layer through the contact hole.

4. A method for manufacturing a semiconductor device, comprising the steps of:

forming an oxide semiconductor stack including a first oxide semiconductor layer, a second oxide semiconductor layer over the first oxide semiconductor layer, and a third oxide semiconductor layer over the second oxide semiconductor layer, wherein the second oxide semiconductor layer has a smaller energy gap than the first oxide semiconductor layer, and the third oxide semiconductor layer has a larger energy gap than the second oxide semiconductor layer;

forming a source electrode layer and a drain electrode layer over the oxide semiconductor stack;

forming a gate insulating film over the source electrode layer and the drain electrode layer;

introducing oxygen into the oxide semiconductor stack with use of the source electrode layer and the drain electrode layer as a mask; and

forming a gate electrode layer overlapping the oxide semiconductor stack with the gate insulating film interposed therebetween.

5. The method for manufacturing a semiconductor device according to claim 4,

wherein the third oxide semiconductor layer covers a side surface of the first oxide semiconductor layer and a side surface of the second oxide semiconductor layer.

6. The method for manufacturing a semiconductor device according to claim 4, further comprising a step of introducing dopant into the oxide semiconductor stack with use of the gate electrode layer as a mask.

7. The method for manufacturing a semiconductor device according to claim 4, further comprising steps of:

forming an interlayer insulating film over the gate electrode layer;

forming a contact hole in the interlayer insulating film so as to reach at least one of the source electrode layer and the drain electrode layer; and

forming a wiring layer over the interlayer insulating film, wherein the wiring layer is connected to the at least one of the source electrode layer and the drain electrode layer through the contact hole.