Metal oxide TFT with improved source/drain contacts and reliability

• US 9,768,322 B2
• Filed: 08/01/2016
• Issued: 09/19/2017
• Est. Priority Date: 06/08/2011
• Status: Active Grant

• Current Assignee: Fantasy Shine Limited
• Original Assignee: CBRITE Inc.
• Inventors: Yu, Gang, Shieh, Chan-Long, Xiao, Tian, Foong, Fatt
• Primary Examiner(s): Nicely, Joseph C
• Application Number:
  US15/225,592
• Publication Number:
  US 20170033227A1
• Time in Patent Office: 414 Days
• CPC Class Codes: H01L 21/321 After treatment
• CPC Class Codes: H01L 21/324 Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering H01L21/20 - H01L21/288 and H01L21/302 - H01L21/322 take precedence
• CPC Class Codes: H01L 21/383 using diffusion into or out of a solid from or into a gaseous phase
• CPC Class Codes: H01L 21/428 using electromagnetic radiation, e.g. laser radiation
• CPC Class Codes: H01L 21/44 Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/38 - H01L21/428
• CPC Class Codes: H01L 21/47635 After-treatment of these layers
• CPC Class Codes: H01L 21/477 Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering H01L21/38 - H01L21/449 and H01L21/461 - H01L21/475 take precedence
• CPC Class Codes: H01L 21/823418 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 23/3171 the coating being directly applied to the semiconductor body, e.g. passivation layer H01L23/3178 takes precedence
• CPC Class Codes: H01L 23/564 Details not otherwise provided for, e.g. protection against moisture getters H01L23/26
• CPC Class Codes: H01L 29/45 Ohmic electrodes
• CPC Class Codes: H01L 29/4908 for thin film semiconductor, e.g. gate of TFT
• CPC Class Codes: H01L 29/66742 Thin film unipolar transistors
• CPC Class Codes: H01L 29/66969 of devices having semiconductor bodies not comprising group 14 or group 13/15 materials comprising selenium or tellurium in uncombined form other than as impurities in semiconductor bodies of other materials, comprising cuprous oxide or cuprous iodide H01L21/02365
• CPC Class Codes: H01L 29/78606 with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device H01L29/78642, H01L29/78645 take precedence
• CPC Class Codes: H01L 29/78618 characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure silicide contacts, electrodes in general H01L29/458
• CPC Class Codes: H01L 29/78648 arranged on opposing sides of the channel
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 : Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A method including providing a substrate with a gate, a layer of gate insulator material adjacent the gate, and a layer of metal oxide semiconductor material positioned on the gate insulator opposite the gate, forming a selectively patterned etch stop passivation layer and heating at elevated temperature in an oxygen-containing or nitrogen-containing or inert ambience to selectively increase the carrier concentration in regions of the metal oxide semiconductor not covered by the etch stop layer, on which overlying and spaced apart source/drain metals are formed. Subsequently heating the transistor in an oxygen-containing or nitrogen-containing or inert ambience to further improve the source/drain contacts and adjust the threshold voltage to a desired level. Providing additional passivation layer(s) on top of the transistor with electric insulation and barrier property to moisture and chemicals in the surrounding environment.

Claims

1. A stable metal oxide semiconductor thin film transistor with ohmic source/drain contacts and high reliability comprising:

a substrate with a gate, a layer of gate insulator adjacent the gate, and a layer of metal oxide semiconductor material positioned on the layer of gate insulator opposite the gate; and

,

a patterned etch stop passivation layer on selected portions of the layer of metal oxide semiconductor material defining not covered source/drain areas, the carrier concentration in the source/drain areas of the metal oxide semiconductor not covered by the etch stop layer being increased by heating together with all underlying layers at elevated temperature in an oxygen-containing or nitrogen-containing or inert ambience;

overlying and spaced apart source/drain metals formed on the source/drain areas, respectively, to make ohmic contact in a thin film transistor configuration;

the thin film transistor on the substrate being heated in an oxygen-containing or nitrogen-containing or inert ambience to further improve the source/drain contacts and adjust the threshold voltage to desired level; and

additional passivation layer(s) positioned on top of the thin film transistor with electric insulation and barrier property to moisture and chemicals in the surrounding environment.

2. A stable metal oxide semiconductor thin film transistor as claimed in claim 1, wherein the substrate is a glass, stainless steel or plastic sheet.

3. A stable metal oxide semiconductor thin film transistor as claimed in claim 1, wherein the substrate is one of rigid or flexible.

4. A stable metal oxide semiconductor thin film transistor as claimed in claim 1, wherein the gate metal layer or source/drain metal layer comprises at least one of Mo, Al, Cu, Ti, Nd, or their combinations in stack or in alloy blend.

5. A stable metal oxide semiconductor thin film transistor as claimed in claim 1, wherein the gate insulator layer comprises at least one of SiN_x:

H, SiO_x;

H, SiON_x;

H, Al₂O₃;

H, HfO₂;

H, ZrO₂;

H, or their combinations in stack or in composite/blend form.

6. A stable metal oxide semiconductor thin film transistor as claimed in claim 1, wherein the transistor is incorporated into thin film circuit applications including active matrix displays, image sensor arrays, touch sensor arrays, proximity sensing arrays, biosensor arrays, chemical sensor arrays and electronic arrays with multiple functionalities based on combinations above.

7. A stable metal oxide semiconductor thin film transistor as claimed in claim 6, wherein the active matrix displays are active matrix liquid crystal displays, active matrix organic light emitting displays, active matrix inorganic light emitting displays, active matrix electrophoretic displays.

8. A stable metal oxide semiconductor thin film transistor as claimed in claim 6, wherein the image sensor array is an X-ray image array.

9. A stable metal oxide semiconductor thin film transistor as claimed in claim 1, wherein the layer of metal oxide semiconductor material includes a single layer of metal oxide semiconductor material with a carrier concentration in a range of 10¹²-10¹⁸ electrons/cm³.

10. A stable metal oxide semiconductor thin film transistor as claimed in claim 1, wherein the layer of metal oxide semiconductor material includes a dual overlying sub-layer of metal oxide semiconductor material with a carrier concentration in a range of 10¹⁷-10¹⁹ electrons/cm³ in the sub-layer adjacent to the layer of gate insulator and a carrier concentration <

10¹⁷ electrons/cm³ in the sub-layer adjacent an upper surface of the sub-layer.

11. A stable metal oxide semiconductor thin film transistor as claimed in claim 1, wherein the layer of metal oxide semiconductor material includes a multiple sub-layer of metal oxide semiconductor material with a carrier concentration in a range of 10¹⁷-10¹⁹ electrons/cm³ in a first sub-layer adjacent to the layer of gate insulator and a carrier concentration <

10¹⁷ electrons/cm³ in an upper sub-layer in contact with the passivation layer.

12. A stable metal oxide semiconductor thin film transistor as claimed in claim 1, wherein the patterned etch stop passivation layer is an inorganic insulator.

13. A stable metal oxide semiconductor thin film transistor as claimed in claim 12, wherein the inorganic insulator is selected from one of SiO₂, SiON, Al₂O₃, Ta₂O₅, TiO₂, MgO, B₂O₃, ZrO₂, Y₂O₃, HfO₂, V₂O₅, Nb₂O₅, La₂O₃, Sc₂O₃, and combinations thereof.

14. A stable metal oxide semiconductor thin film transistor as claimed in claim 1, wherein the source/drain metal contacts include a low work function metal portion and a high work function barrier metal portion, the work function of the low work function metal being one of equal to and lower than a work function of the metal oxide semiconductor active layer, and the work function of the high work function barrier metal being one of equal to and greater than the work function of the metal oxide semiconductor active layer, the low work function metal portion being positioned on the metal oxide semiconductor active layer, and the high work function barrier metal portion being positioned on the low work function metal portion.

15. A stable metal oxide semiconductor thin film transistor as claimed in claim 14, wherein the low work function metal includes one of Al, Mg, Ti, Ta, Zn, In, V, Hf, Y or an alloy comprising them.

16. A stable metal oxide semiconductor thin film transistor as claimed in claim 14, wherein the high work function barrier metal includes one of Mo, W, Au, Pt, Ag, Cu, Cr, Ni or an alloy comprising them.

17. A stable metal oxide semiconductor thin film transistor as claimed in claim 14, wherein the additional passivation layer(s) positioned on top of the thin film transistor comprises at least one of SiN_x, SiO_xN_y, AlN, Al₂O₃, SiAlON, TaO_x, TiO₂, organic material including one of polyimide, PMMA, PMGI, polysilane, polysiloxane, spin-on-glass, SAM, surface promoters or commercially available photoresists used as planarization layer or bank layer used in display field, or their combinations in stack or in composite/blend form.