Aging-based leakage energy reduction method and system

• US 9,768,767 B2
• Filed: 10/28/2016
• Issued: 09/19/2017
• Est. Priority Date: 01/06/2013
• Status: Expired due to Fees

• Current Assignee: Empire Technology Development LLC (Allied Inventors Management, LLC), Regents of the University of California (University of California)
• Original Assignee: Empire Technology Development LLC (Allied Inventors Management, LLC)
• Inventors: Potkonjak, Miodrag
• Primary Examiner(s): Cole, Brandon S
• Application Number:
  US15/336,808
• Publication Number:
  US 20170047920A1
• Time in Patent Office: 326 Days
• Field of Search: 327524-602
• CPC Class Codes: G06F 2119/04 Ageing analysis or optimisation against ageing
• CPC Class Codes: G06F 2119/06 Power analysis or power optimisation
• CPC Class Codes: G06F 2119/12 Timing analysis or timing optimisation
• CPC Class Codes: G06F 30/30 Circuit design
• CPC Class Codes: H01L 21/28 Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268 etching for patterning the electrodes H01L21/311, H01L21/3213; multistep manufacturing processes for data storage electrodes H01L29/4011
• CPC Class Codes: H01L 21/326 Application of electric currents or fields, e.g. for electroforming H01L21/20 - H01L21/288 and H01L21/302 - H01L21/324 take precedence
• CPC Class Codes: H01L 21/823437 with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
• CPC Class Codes: H01L 22/14 for electrical parameters, e.g. resistance, deep-levels, CV, diffusions by electrical means
• CPC Class Codes: H01L 22/20 Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
• CPC Class Codes: H01L 29/408 with an insulating layer with a particular dielectric or electrostatic property, e.g. with static charges or for controlling trapped charges or moving ions, or with a plate acting on the insulator potential or the insulator charges, e.g. for controlling charges effect or potential distribution in the insulating layer, or with a semi-insulating layer contacting directly the semiconductor surface
• CPC Class Codes: H03K 17/161 in field-effect transistor switches
• CPC Class Codes: H03K 2217/0036 Means reducing energy consumption

Abstract

A technique of reducing leakage energy associated with a post-silicon target circuit is generally described herein. One example method includes purposefully aging a plurality of gates in the target circuit based on a targeted metric including a timing constraint associated with the target circuit.

Claims

1. A method to reduce leakage energy associated with a post-silicon target circuit, the method comprising:

determining an extent to which a plurality of gates in the target circuit is to be aged based on a targeted metric that includes a timing constraint associated with the target circuit;

based on the targeted metric, aging, to the determined extent, a first set of gates of the plurality of gates;

based on the targeted metric, aging, to less than the determined extent, a second set of gates of the plurality of gates; and

based on the targeted metric, applying an adaptive body bias (ABB) to the target circuit.

2. The method of claim 1, further comprising characterizing the plurality of gates at a transistor or gate level.

3. The method of claim 1, further comprising assigning a first weight and a second weight to each gate in the target circuit based on a contribution of each gate to energy consumption and critical timing constraints associated with the target circuit, wherein the first weight is associated with the leakage energy, and wherein the second weight is associated with timing.

4. A method to reduce leakage energy associated post-silicon target circuit, the method comprising:

assigning a first weight and a second weight to each gate in the target circuit based on a contribution of each gate to energy consumption and critical timing constraints associated with the target circuit, wherein the first weight is associated with the leakage energy, and wherein the second weight is associated with timing;

formulating a satisfiability (SAT) problem that includes a first set of objectives for a first set of gates and a second set of objectives for a second set of gates to reduce the leakage energy associated with the target circuit;

selecting a set of candidate input vectors for the target circuit through an iterative solution of the SAT problem by removal of one or more gates from being considered in the first set of objectives and the second set of objectives based on the first weight and the second weight;

based on a targeted metric that includes a timing constraint associated with the target circuit, determining an extent to which a plurality of gates, which includes the first set of gates and the second set of gates, in the target circuit is to be aged;

based on the targeted metric, applying the selected set of candidate input vectors to age, to the determined extent, the first set of gates of the plurality of gates; and

based on the targeted metric, applying in the selected set of candidate input vectors to age, to less than the determined extent, the second set of gates of the plurality of gates.

5. The method of claim 4, further comprising selecting a subset of input vectors from the selected set of candidate input vectors such that the timing constraint associated with the target circuit is satisfied.

6. The method of claim 5, further comprising setting the timing constraint in a linear program that includes an objective to reduce leakage energy associated with a certain set of gates of the plurality of gates.

7. The method of claim 6, further comprising approximating a possible critical path in the target circuit based on an initial longest path in terms of delays associated with a subset of gates along the initial longest path.

8. A non-transitory computer-readable medium that includes instructions to reduce leakage energy associated with a post-silicon target circuit, wherein the instructions, in response to execution by a processor, cause the processor to perform or control performance of operations to:

determine an extent to which a plurality of gates in the target circuit is to be aged based on a targeted metric that includes a timing constraint associated with the target circuit;

based on the targeted metric, age, to the determined extent, a first set of gates of the plurality of gates;

based on the targeted metric, age, to less than the determined extent, a second set of gates of the plurality of gates; and

based on the targeted metric, apply an adaptive body bias (ABB) to the target circuit.

9. The non-transitory computer readable medium of claim 8, wherein the instructions comprise instructions, which in response to execution by the processor, cause the processor to perform or control performance of at least one operation to:

characterize the plurality of gates at a transistor or gate level.

10. The non-transitory computer readable medium of claim 8, wherein the instructions comprise instructions, which in response to execution by the processor, cause the processor to perform or control performance of at least one operation to:

assign a first weight and a second weight to each gate in the target circuit based on a contribution of each gate to energy consumption and critical timing constraints associated with the target circuit, wherein the first weight is associated with the leakage energy, and wherein the second weight is associated with timing.

11. The non-transitory computer readable medium of claim 10, wherein the instructions comprise instructions, which in response to execution by the processor, cause the processor to perform or control performance of at least one operation to:

formulate a satisfiability (SAT) problem that includes a first set of objectives for the first set of gates of the plurality of gates and a second set of objectives for the second set of gates of the plurality of gates to reduce the leakage energy associated with the target circuit; and

select a set of candidate input vectors for the target circuit through an iterative solution of the SAT problem by removal of one or more gates from being considered in the first set of objectives and the second set of objectives based on the first weight and the second weight,

wherein to age, to the determined extent, the first set of gates of the plurality of gates, and to age, to less than the determined extent, the second set of gates of the plurality of gates, the instructions, in response to execution by the processor, cause the processor to perform or control performance of at least one operation to;

apply the set of candidate input vectors to the plurality of gates to stress the plurality of gates.

12. The non-transitory computer readable medium of claim 11, wherein the instructions comprise instructions, which in response to execution by the processor, cause the processor to perform or control performance of at least one operation to:

select a subset of input vectors from the set of candidate input vectors such that the timing constraint associated with the target circuit is satisfied.

13. The non-transitory computer readable medium of claim 12, wherein the instructions comprise instructions, which in response to execution by the processor, cause the processor to perform or control performance of at least one operation to:

set the timing constraint in a linear program that includes an objective to reduce leakage energy associated with a certain set of gates of the plurality of gates.

14. The non-transitory computer readable medium of claim 13, wherein the instructions comprise instructions, which in response to execution by the processor, cause the processor to perform or control performance of at least one operation to:

approximate a possible critical path in the target circuit based on an initial longest path in terms of delays associated with a subset of gates along the initial longest path.

15. A computing device coupled to a post-silicon target circuit and configured to reduce leakage energy associated with the post-silicon target circuit, the computing device comprising:

a programmable unit; and

a processor, a operatively coupled to the programmable unit, wherein the processor is configured to;

determine an extent to which a plurality of gates in the target circuit is to be aged based on a targeted metric that includes a timing constraint associated with the target circuit;

based on the targeted metric, age, to the determined extent, a first set of gates of the plurality of gates;

based on the targeted metric, age, to less than the determined extent, a second set of gates of the plurality of gates; and

based on the targeted metric, apply an adaptive body bias (ABB) to the target circuit.

16. The computing device of claim 15, wherein the processor is further configured to characterize the plurality of gates at a transistor or gate level.

17. The computing device of claim 15, wherein the processor is further configured to:

assign a first weight and a second weight to each gate in the target circuit based on a contribution of each gate to energy consumption and critical timing constraints of the target circuit, wherein the first weight is associated with the leakage energy, and wherein the second weight is associated with timing.

18. A computing device coupled to a post-silicon target circuit and configured to reduce leakage energy associated with the post-silicon target circuit, the computing device comprising:

a programmable unit; and

a processor, operatively coupled to the programmable unit, wherein the processor is configured to;

assign a first weight and a second weight to each gate in the target circuit based on a contribution of each gate to energy consumption and critical timing constraints associated with the target circuit, wherein the first weight is associated with the leakage energy, and wherein the second weight is associated with timing;

formulate a satisfiability (SAT) problem that includes a first set of objectives for a first set of gates and a second set of objectives for a second set of gates to reduce the leakage energy associated with the target circuit;

select a set of candidate input vectors for the target circuit through an iterative solution of the SAT problem by removal of one or more gates from being considered in the first set of objectives and the second set of objectives based on the first weight and the second weight;

based on a targeted metric that includes a timing constraint associated with the target circuit, determine an extent to which a pluralitv of gates, which includes the first set of gates and the second set of gates, in the target circuit is to be aged;

based on the targeted metric, apply the selected set of candidate input vectors to age, to the determined extent, the first set of gates of the plurality of gates; and

based on the targeted metric, apply the selected set of candidate input vectors to age, to less than the determined extent, the second set of gates of the plurality of gates.

19. The computing device of claim 18, wherein the processor is configured to select a subset of input vectors from the set of candidate input vectors such that the timing constraint associated with the target circuit is satisfied.

20. The computing device of claim 19, wherein the processor is further configured to set the timing constraint in a linear program that includes an objective to reduce leakage energy associated with a certain set of gates of the plurality of gates.

21. The computing device of claim 20, wherein the processor is further configured to approximate a possible critical path in the target circuit based on an initial longest path in terms of delays associated with a subset of gates along the initial longest path.