Polarity adaptive power source apparatus

• US 9,768,772 B1
• Filed: 08/14/2014
• Issued: 09/19/2017
• Est. Priority Date: 08/14/2014
• Status: Active Grant

• Current Assignee: Amazon Technologies, Inc. (Amazon.com, Inc.)
• Original Assignee: Amazon Technologies, Inc. (Amazon.com, Inc.)
• Inventors: Khamashta, Robert, Hershey, Daniel David, Goulden, Jason Evans, Doblack, Shelomon Patrick, Deeds, III, Manuel Rinley, Su, Hsueh Jang, Zhou, Mi, Cederlof, Colter Earl
• Primary Examiner(s): Fureman, Jared
• Assistant Examiner(s): YESHAW, ESAYAS G
• Application Number:
  US14/460,049
• Time in Patent Office: 1,132 Days
• CPC Class Codes: H02M 1/10 Arrangements incorporating converting means for enabling loads to be operated at will from different kinds of power supplies, e.g. from ac or dc
• CPC Class Codes: H02M 7/5387 in a bridge configuration
• CPC Class Codes: H03K 17/6871 the output circuit comprising more than one controlled field-effect transistor
• CPC Class Codes: H03K 17/94 characterised by the way in which the control signals are generated

Abstract

Described are devices for automatically adapting electrical polarity from a power source to a specified output polarity for use by an electrical load. In one implementation, power adaptation circuitry comprising one or more bridge circuits accept electrical power of unspecified polarity and output specified polarity. The bridge circuit may comprise a plurality of field-effect transistors (FETs) configured such that a particular subset of the FETs are energized to conduct electric current to the outputs when a particular polarity is applied at inputs.

Claims

1. A device comprising:

a battery receptacle comprising a first contact and a second contact configured to electrically couple to a battery in either a first orientation or a second orientation with respect to polarity of the battery;

a bridge circuit connected to the first contact and the second contact and having a positive output and a negative output, the bridge circuit comprising;

four metal oxide semiconductor field-effect transistors (MOSFETs) Q1, Q2, Q3, and Q4, wherein;

the Q1 and the Q4 comprise N-type MOSFETs each having a source, gate, and drain;

the Q2 and the Q3 comprise P-type MOSFETs each having a source, gate, and drain;

the first contact is connected to the drains of the Q1 and the Q3 and the gates of the Q4 and the Q2;

the second contact is connected to the drains of the Q4 and the Q2 and the gates of the Q1 and the Q3;

the sources of the Q1 and the Q4 are connected to the negative output; and

the sources of the Q2 and the Q3 are connected to the positive output.

2. The device of claim 1, wherein the four MOSFETs are configured to exhibit a gate threshold voltage (V_GS) less than or equal to a minimum working voltage of the battery.

3. The device of claim 1, wherein:

the battery receptacle comprises a first receptacle;

the bridge circuit comprises a first bridge circuit;

the positive output comprises a first positive output;

the negative output comprises a first negative output; and

the device further comprising;

a second receptacle connected to a second bridge circuit; and

wherein;

the first negative output of the first bridge circuit is connected to a second positive output of the second bridge circuit; and

the first positive output and the second negative output are configured to connect to a load.

4. The device of claim 1, further comprising:

power monitor circuitry configured to provide information indicative of operation of one or more of the Q1, the Q2, the Q3, or the Q4 to a processor.

5. A device comprising:

a bridge circuit having a first input, a second input, a first output, and a second output, the bridge circuit comprising;

a first field-effect transistor (FETs), a second FET, a third FET, and a fourth FET fourth FET;

wherein;

the first FET and the fourth FET comprise FETs each having a source, a gate, and a drain, wherein the first FET and the fourth FET comprise N-type FETs;

the second FET and the third FET comprise FETs each having a source, a gate, and a drain, wherein the second FET and the third FET comprise P-type FETs;

the first input is connected to;

the drains of the first FET and the third FET, and

the gates of the second FET and the fourth FET;

the second input is connected to;

the drains of the second FET and the fourth FET, and

the gates of the first FET and the third FET;

the sources of the first FET and the fourth FET are connected to the second output; and

the sources of the second FET and the third FET are connected to the first output.

6. The device of claim 5, wherein the FETs comprise semiconductor materials configured to exhibit a gate threshold voltage (V_GS) of at least 0.4 Volts (V).

7. The device of claim 5, further comprising:

a receptacle connected to the first input and the second input of the bridge circuit, the receptacle configured to couple to a power source in a plurality of physical orientations.

8. The device of claim 5, the power source comprising one or more battery cells configured to provide a maximum cell output voltage of 2 volts across the first input and the second input.

9. The device of claim 5, further comprising a first palindromic connector having a first conductor connected to the first input and a second conductor connected to the second input of the bridge circuit, wherein the first palindromic connector is configured to couple to a second palindromic connector.

10. The device of claim 5, further comprising an indicator circuit coupled to the first output and the second output, the indicator circuit configured to provide one or more of an audible or a visual indication that the bridge circuit is or is not providing power at the second output and the first output.

11. The device of claim 5, further comprising:

power monitor circuitry configured to provide, to a processor, information indicative of operation of one or more of the first FET, the second FET, the third FET, or the fourth FET of the bridge circuit.

12. A device comprising:

a first field effect transistor (FET) and a second FET, each having a source, gate, and a drain, wherein the first FET and the second FET comprise N-type FETs;

a third FET and a fourth FET, each having a source, gate, and a drain, wherein the third FET and the fourth FET comprise P-type FETs;

a first input connected to the drains of the first FET and the fourth FET and the gates of the second FET and the third FET; and

a second input connected to the drains of the second FET and the third FET and the gates of the first FET and the fourth FET;

wherein;

the sources of the first FET and the second FET are connected to a negative output; and

the sources of the third FET and the fourth FET are connected to a positive output.

13. The device of claim 12, wherein the FETs are configured to exhibit a gate threshold voltage (V_GS) greater than or equal to a minimum discharge voltage of a power source.

14. The device of claim 12, wherein the FETs comprise semiconductor materials configured to exhibit a gate threshold voltage (V_GS) of at least 0.4 Volts (V).

15. The device of claim 12, wherein the FETs are configured to exhibit a drain-to-source on-resistance (R_DS(on)) of less than 250 milliohms.

16. The device of claim 12, further comprising:

power monitor circuitry configured to provide information indicative of operation of one or more of the first FET, the third FET, the fourth FET, or the second FET to a processor.

17. The device of claim 12, further comprising a battery receptacle configured to establish electrical contact with a battery in a plurality of orientations;

wherein a first terminal of the battery receptacle connects to the first input and a second terminal of the battery receptacle connects to the second input.

18. The device of claim 12, further comprising a connector configured to establish electrical contact between a power source and the first input and the second input.

19. The device of claim 12, further comprising a first palindromic connector having a first conductor connected to the first input and a second conductor connected to the second input, wherein the first palindromic connector is configured to couple to a second palindromic connector.

20. The device of claim 12, further comprising an indicator circuit coupled to the negative output and the positive output, the indicator circuit configured to provide one or more of an audible or a visual indication that the bridge circuit is one or more of:

providing power or not providing power, at the positive output and the negative output.