Dual voltage supply

• US 9,768,773 B2
• Filed: 01/27/2016
• Issued: 09/19/2017
• Est. Priority Date: 01/27/2016
• Status: Active Grant

• Current Assignee: pSemi Corporation (Murata Manufacturing Co Limited)
• Original Assignee: Peregrine Semiconductor Corporation (Murata Manufacturing Co Limited)
• Inventors: Englekirk, Robert Mark
• Primary Examiner(s): CRAWFORD, JASON
• Application Number:
  US15/007,847
• Publication Number:
  US 20170214402A1
• Time in Patent Office: 601 Days
• Field of Search: 326 56- 58
• CPC Class Codes: H01C 1/16 Resistor networks not otherwise provided for
• CPC Class Codes: H03F 1/0211 with control of the supply voltage or current
• CPC Class Codes: H03F 3/45 Differential amplifiers differential sense amplifiers G11C7/062
• CPC Class Codes: H03K 19/0002 Multistate logic H03K19/02 takes precedence

Abstract

A system, comprising a dual voltage supply configured to receive a logic state input voltage and configured to output an output voltage, wherein the dual voltage supply is configured to output a nominal voltage at a high state of the logic state input voltage and the dual voltage supply is configured to output a high voltage at a low state of the logic state input voltage, a pre-charge capacitor is configured to receive the output voltage of the dual voltage supply and an output buffer has an output buffer power input is coupled to the pre-charge capacitor and configured to receive the output voltage of the dual voltage supply, an output buffer signal input is configured to receive the logic state input voltage and an output buffer output is configured to output a digital output signal.

Claims

1. A system, comprising:

a dual voltage supply configured to receive a logic state input voltage and configured to output an output voltage, wherein the dual voltage supply is configured to output a nominal voltage at a high state of the logic state input voltage and the dual voltage supply is configured to output a high voltage at a low state of the logic state input voltage;

a pre-charge capacitor configured to receive the output voltage of the dual voltage supply; and

an output buffer has an output buffer power input coupled to the pre-charge capacitor and configured to receive the output voltage of the dual voltage supply, an output buffer signal input configured to receive the logic state input voltage and an output buffer output configured to output a digital output signal.

2. The system of claim 1, wherein the output buffer is a tristate buffer configured to also receive a tristate control signal.

3. The system of claim 1, wherein the dual voltage supply comprises:

an inverter has an inverter input configured to receive the logic state input voltage;

a nominal switch has a nominal switch actuator coupled the inverter input, a nominal switch first pole is configured to receive the nominal voltage;

a high switch has a high switch actuator coupled to an inverter output of the inverter, a high switch first pole is configured to receive the high voltage, a high switch second pole is coupled to a nominal switch second pole; and

wherein the output buffer has the output buffer power input coupled to the high switch second pole.

4. The system of claim 3, wherein the nominal switch comprises a transistor.

5. The system of claim 3, wherein the high switch comprises a transistor.

6. The system of claim 1, wherein the dual voltage supply comprises:

an input buffer configured to receive the logic state input voltage;

a nominal transistor has a nominal transistor gate coupled to an output of the input buffer, a nominal transistor drain configured to receive the nominal voltage;

an inverter has an inverter input coupled to the output of the input buffer;

a high transistor has a high transistor gate coupled to an inverter output of the inverter, a high transistor drain configured to receive the high voltage, a high transistor source coupled to a nominal transistor source of the nominal transistor; and

wherein the output buffer has the output buffer power input coupled to the nominal transistor drain of the nominal transistor.

7. The system of claim 6, wherein the nominal transistor is n-type.

8. The system of claim 6, wherein the nominal transistor is p-type.

9. The system of claim 6, wherein the high transistor is n-type.

10. The system of claim 6, wherein the high transistor is p-type.

11. A system comprising:

at least three voltage dividing resistors coupled in series;

a voltage divider switch coupled across at least one of the at least three voltage dividing resistors, said voltage divider switch configured to receive a logic state input voltage;

a differential amplifier has a first differential amplifier input coupled to at least one of the at least three voltage dividing resistor and a second differential amplifier input configured to receive a reference voltage;

a power gating transistor has a power gating gate coupled to a differential amplifier output of the differential amplifier, a power gating drain configured to be coupled to a power source and a power gating source coupled to one of the at least three voltage dividing resistors;

a pre-charge capacitor coupled to the power gating source of the power gating transistor; and

an output buffer configured to receive power from the source of the power gating transistor and the pre-charge capacitor, an output buffer signal input configured to receive the logic state input voltage and an output buffer signal output configured to output a digital output signal.

12. The system of claim 11, wherein the output buffer is a tristate buffer configured to also receive a tristate control signal.

13. The system of claim 11, wherein the at least three voltage dividing resistors comprise resistor networks having selectable resistors.

14. The system of claim 11, wherein the power gating transistor is n-type.

15. The system of claim 11, wherein the power gating transistor is p-type.

16. The system of claim 11, wherein the voltage divider switch comprises a transistor.

17. A system comprising:

at least one third resistor;

a power gating transistor has a power gating drain configured to be coupled to a power source and a power gating source coupled to the at least one third resistor;

a pull up transistor has a pull up gate configured to receive a logic state input voltage, a pull up source coupled to a first end of the at least one third resistor;

a differential amplifier has a first input coupled to a reference voltage and a differential amplifier output coupled to a power gating gate of the power gating transistor; and

an output buffer has an input buffer power input configured to receive the output voltage, an output buffer signal input configured to receive the logic state input voltage and an output buffer signal output configured to output a digital output signal.

18. The system of claim 17, wherein the at least one third resistor comprises a third resistor network having a plurality of series coupled third resistors and a plurality of third switches coupled in parallel with the third resistors selecting designated ones of the plurality of third resistors.

19. The system of claim 17, wherein the at least one third resistor comprises a third resistor network having a plurality of parallel coupled third resistors and a plurality of third switches coupled in series with the third resistors selecting designated ones of the plurality of third resistors.

20. The system of claim 17 wherein the output buffer is a tristate buffer has a second output buffer signal input configured to receive a tristate control signal.

21. The system of claim 17, further comprising a pre-charge capacitor coupled to the power gating source of the power gating transistor.

22. The system of claim 17 further comprising:

at least one first resistor;

at least one second resistor in series connection to the at least one first resistor and the at least one second resistor in series connection to the at least one third resistor;

a pull up drain of the pull up transistor coupled to a junction of the at least one second resistor and the at least one third resistor;

a second input of the differential amplifier coupled to a juncture of the at least one first resistor and the at least one second resistor; and

a pre-charge capacitor configured to receive the output voltage and coupled to the output buffer power input.

23. The system of claim 22, wherein the at least one third resistor comprises a third resistor network having a plurality of series coupled third resistors and a plurality of third switches coupled in parallel across the third resistors selecting designated ones of the plurality of third resistors.

24. The system of claim 22, wherein the at least one third resistor comprises a third resistor network having a plurality of parallel coupled third resistors and a plurality of third switches coupled in series to the third resistors selecting designated ones of the plurality of third resistors.

25. The system of claim 22, wherein the at least one first resistor comprises a first resistor network having a plurality of series coupled first resistors and a plurality of first switches coupled in parallel across the first resistors selecting designated ones of the plurality of first resistors.

26. The system of claim 22, wherein the at least one first resistor comprises a first resistor network having a plurality of parallel coupled first resistors and a plurality of first switches coupled in series to the first resistors selecting designated ones of the plurality of first resistors.

27. The system of claim 22, wherein the at least one second resistor comprises a second resistor network having a plurality of series coupled second resistors and a plurality of second switches coupled in parallel across the second resistors selecting designated ones of the plurality of second resistors.

28. The system of claim 22, wherein the at least one second resistor comprises a second resistor network having a plurality of parallel coupled second resistors and a plurality of second switches coupled in series to the second resistors selecting designated ones of the plurality of second resistors.

29. A method comprising:

a) establishing a digital output buffer having a buffer input, a buffer output and a buffer power connection;

b) pre-charging a pre-charge capacitor coupled to the buffer power connection to one of a high state upon receiving a low logic state input voltage at the buffer input and a nominal state upon receiving a high logic state input voltage at the buffer input; and

c) utilizing the charge stored on the pre-charge capacitor to drive the buffer output.

30. A method comprising:

a) establishing a digital output buffer having a buffer input, a buffer output and a buffer power connection;

b) selecting two resistor division ratios to set a sense signal;

c) pre-charging a pre-charge capacitor coupled to the buffer power connection based on the sense signal; and

d) utilizing the charge stored on the pre-charge capacitor to drive the buffer output.