Apparatus and method for conversion between analog and digital domains with a time stamp for a digital control system and ultra low error rate communications channel

• US 9,768,814 B1
• Filed: 10/09/2015
• Issued: 09/19/2017
• Est. Priority Date: 09/16/2010
• Status: Active Grant

• Current Assignee: Benjamin J. Sheahan
• Original Assignee: Benjamin J. Sheahan
• Inventors: Sheahan, Benjamin J.
• Primary Examiner(s): Cadeau, Wednel
• Application Number:
  US14/879,965
• Time in Patent Office: 711 Days
• CPC Class Codes: H03M 1/004 Reconfigurable analogue/digital or digital/analogue converters H03M1/02 takes precedence
• CPC Class Codes: H03M 1/0624 by synchronisation
• CPC Class Codes: H03M 1/361 having a separate comparator and reference value for each quantisation level, i.e. full flash converter type
• CPC Class Codes: H03M 1/745 with weighted currents
• CPC Class Codes: H04B 1/38 Transceivers, i.e. devices in which transmitter and receiver form a structural unit and in which at least one part is used for functions of transmitting and receiving
• CPC Class Codes: H04B 10/07953 Monitoring or measuring OSNR, BER or Q
• CPC Class Codes: H04L 1/0001 Systems modifying transmission characteristics according to link quality, e.g. power backoff adaptive data allocation for multicarrier modulation H04L5/0044; controlling transmission power for radio systems H04W52/04
• CPC Class Codes: H04L 1/0054 Maximum-likelihood or sequential decoding, e.g. Viterbi, Fano, ZJ algorithms

Abstract

An apparatus and method is disclosed with embodiments of a: 1. digital to analog and reference time converter; 2. analog and reference time to digital converter; 3. Sheahan non-linear time-varying, analog and digital control system; and 4. Sheahan Communication Channel are described in detail herein. Some embodiments use time stamp having 72 bits of time data sufficient to identify each clock pulse of a 9.192631770 GHz clock signal plus an additional 8 bits representing 2⁸=256 interpolated clock phases in order reach a resolution of approximately 0.425 picoseconds per clock phase. Thus an 80 bit time stamp is generated and used as described herein.

Claims

1. A method for communicating digital data having at least one bit, comprising the steps of:

converting the digital data to analog data at an absolute reference time;

generating a defined absolute reference time stamp representing the absolute reference time;

transmitting the analog data and the defined absolute reference time stamp;

receiving the analog data and the defined absolute reference time stamp;

correcting erroneous signals in the analog data with the defined absolute reference time stamp to improve a bit error rate; and

converting the analog data to digital data.

2. The method for communicating digital data of claim 1, wherein the step of transmitting the analog data and the defined absolute reference time stamp is performed wirelessly.

3. The method for communicating digital data of claim 1, wherein the step of transmitting the analog data and the defined absolute reference time stamp is performed via wired connections.

4. The method for communicating digital data of claim 1, wherein the defined absolute reference time stamp is 80 bits.

5. A method for transmitting digital data having at least one bit, comprising the steps of:

converting the digital data to analog data at an absolute reference time;

generating a defined absolute reference time stamp representing the absolute reference time; and

transmitting the analog data and the defined absolute reference time stamp to improve a bit error rate.

6. The method for communicating digital data of claim 5, wherein the step of transmitting the analog data and the defined absolute reference time stamp is performed wirelessly.

7. The method for communicating digital data of claim 5, wherein the step of transmitting the analog data and the defined absolute reference time stamp is performed via wired connections.

8. The method for communicating digital data of claim 5, wherein the defined absolute reference time stamp is 80 bits.

9. An communications apparatus, comprising:

a receiver, the receiver for receiving analog data converted from digital data at an absolute reference time, the digital data having at least one bit, and a defined absolute reference time stamp, the defined absolute reference time stamp representing the absolute reference time prior to receipt of the analog data and the defined absolute reference time stamp by the receiver;

an error corrector, the error corrector for correcting erroneous signals in the analog data with the defined absolute reference time stamp to improve a bit error rate impacted by at least one of multipath distortion, frequency error, phase noise, timing jitter, timing synchronization error and recovered clock phase error; and

a converter, the converter converting the analog data to digital data.

10. The communications apparatus of claim 9, wherein the receiver receives the analog data and the defined absolute reference time stamp wirelessly.

11. The communications apparatus of claim 9, wherein the receiver receives the analog data and the defined absolute reference time stamp via wired connections.

12. The communications apparatus of claim 9, wherein the defined absolute reference time stamp is 80 bits.