Direct synthesis of OFDM receiver clock

• US 9,769,003 B2
• Filed: 07/09/2015
• Issued: 09/19/2017
• Est. Priority Date: 12/12/2011
• Status: Active Grant

• Current Assignee: John W. Bogdan
• Original Assignee: John W. Bogdan
• Inventors: Bogdan, John W
• Primary Examiner(s): TON, DANG T
• Application Number:
  US14/795,814
• Publication Number:
  US 20150319024A1
• Time in Patent Office: 803 Days
• Field of Search: 370210
• CPC Class Codes: H03H 17/0251 Comb filters
• CPC Class Codes: H03H 17/04 Recursive filters
• CPC Class Codes: H04L 25/0398 Restoration of channel reciprocity
• CPC Class Codes: H04L 27/2647 Arrangements specific to the receiver only equalisation H04L27/01
• CPC Class Codes: H04L 27/2656 Frame synchronisation, e.g. packet synchronisation, time division duplex [TDD] switching point detection or subframe synchronisation
• CPC Class Codes: H04L 27/2657 Carrier synchronisation
• CPC Class Codes: H04L 27/266 Fine or fractional frequency offset determination and synchronisation
• CPC Class Codes: H04L 27/2671 Time domain
• CPC Class Codes: H04L 27/2695 with channel estimation, e.g. determination of delay spread, derivative or peak tracking channel estimation H04L25/0202

Abstract

This application presents a direct data recovery from subspaces or parameters subranges of a received OFDM signal preidentified as corresponding to specific data symbols, by applying adaptive inverse signal transformation (AIST) method for reversing both original data coding and deterministic and random distortions introduced by a transmission channel, wherein both reversals are achieved by the same conversion of the subspaces or parameter subranges into data transmitted originally in order to eliminate an intermediate recovery of signals or parameters transmitted originally within the received OFDM signal. The AIST includes using both amplitudes and gradients of amplitudes of OFDM tone signals.

Claims

1. A method for direct synthesis of receiver clock (DSRC) using an oscillator clock for producing a synthesized clock synchronous to a referencing frame providing frequency and phase transmittal from a frame of a received orthogonal frequency division multiplexing (OFDM) signal, wherein a clock synthesis configuration comprises a phase detector measuring phase errors between the referencing frame and a corresponding frame of the oscillator clock, a programmable control unit (PCU) reading the measured phase errors in order to produce phase amendments, a phase synthesizer applying the phase amendments to the oscillator clock in order to produce the synthesized clock specified by the phase amendments without introducing uncontrolled phase transients;

wherein the DSRC method comprises the steps of;

processing the received OFDM signal in frequency domain in order to recover selected tones from the received OFDM signal,

detecting boundaries of the frame of the received OFDM signal, by utilizing the recovered selected tones,

defining the referencing frame, by utilizing the detections of the boundaries;

measuring the phase errors between the referencing frame and the corresponding frame of the oscillator clock, by utilizing the phase detector;

calculating, using the PCU, predicted phase amendments designed to compensate the measured phase errors, by utilizing preceding the measured phase errors;

calculating, using the PCU, phase tracking errors between a frame of the synthesized clock and the referencing frame, by utilizing the measured phase errors and the predicted phase amendments;

calculating, using the PCU, following said phase amendments designed to minimize following said phase tracking errors, by utilizing the phase tracking errors and following said predicted phase amendments;

applying, using the phase synthesizer, the following phase amendments to the oscillator clock in order to minimize the following phase tracking errors.

2. A method for direct synthesis of receiver clock (DSRC) using an oscillator clock for producing a synthesized clock synchronous to a referencing frame providing frequency and phase transmittal from a frame of a received orthogonal frequency division multiplexing (OFDM) signal, wherein a clock synthesis configuration comprises a phase detector measuring phase errors between the referencing frame and a corresponding frame of the oscillator clock, a programmable control unit (PCU) reading the measured phase errors in order to produce phase amendments, a phase synthesizer applying the phase amendments to the oscillator clock in order to produce the synthesized clock specified by the phase amendments without introducing uncontrolled phase transients;

wherein the DSRC method comprises the steps of;

detecting boundaries of the frame of the received OFDM signal by processing the received OFDM signal or a sub-carrier signal recovered from the received OFDM signal;

wherein a known detection delay occurs between receptions of the boundaries of the frame of the received OFDM signal and the detections of the boundaries of the frame of the received OFDM signal;

defining the referencing frame, by utilizing the detections of the boundaries and the known detection delay;

measuring the phase errors between the referencing frame and the corresponding frame of the oscillator clock, by utilizing the phase detector;

calculating, using the PCU, predicted phase amendments designed to compensate the measured phase errors, by utilizing preceding the measured phase errors;

calculating, using the PCU, phase tracking errors between a frame of the synthesized clock and the referencing frame, by utilizing the measured phase errors and the predicted phase amendments;

calculating, using the PCU, following said phase amendments designed to minimize following said phase tracking errors, by utilizing the phase tracking errors and following said predicted phase amendments;

applying, using the phase synthesizer, the following phase amendments to the oscillator clock in order to minimize the following phase tracking errors.

3. A method for direct synthesis of receiver clock (DSRC) using an oscillator clock for producing a synthesized clock synchronous to a referencing frame providing frequency and phase transmittal from a frame of a received orthogonal frequency division multiplexing (OFDM) signal, wherein a clock synthesis configuration comprises a phase detector measuring phase errors between the referencing frame and a corresponding frame of the oscillator clock, a programmable control unit (PCU) reading the measured phase errors in order to produce phase amendments, a phase synthesizer applying the phase amendments to the oscillator clock in order to produce the synthesized clock specified by the phase amendments without introducing uncontrolled phase transients;

wherein the DSRC method comprises the steps of;

measuring the phase errors by estimating lengths differences between periods of the referencing frame and corresponding nominal periods of the frame of the oscillator clock;

wherein each of the nominal periods is defined by a number of such oscillator clocks expected to occur during a corresponding period of the referencing frame when the oscillator clock has a predefined frequency relation to the frame of the OFDM signal;

calculating, using the PCU, predicted phase amendments designed to compensate pro-actively the measured phase errors, by utilizing preceding the measured phase errors;

calculating, using the PCU, phase tracking errors between a frame of the synthesized clock and the referencing frame, by utilizing the measured phase errors and the predicted phase amendments;

calculating, using the PCU, following said phase amendments designed to minimize following said phase tracking errors, by utilizing the phase tracking errors and following said predicted phase amendments;

applying, using the phase synthesizer, the following phase amendments to the oscillator clock in order to minimize the following phase tracking errors.