Low power asynchronous counters in a synchronous system

• US 9,772,648 B2
• Filed: 10/20/2015
• Issued: 09/26/2017
• Est. Priority Date: 10/20/2014
• Status: Active Grant

• Current Assignee: Ambiq Micro, Inc.
• Original Assignee: Ambiq Micro, Inc.
• Inventors: Sheafor, Stephen James
• Primary Examiner(s): Huynh, Kim
• Assistant Examiner(s): Browne, Aaron J
• Application Number:
  US14/918,406
• Publication Number:
  US 20160109901A1
• Time in Patent Office: 707 Days
• Field of Search: 713400, 713500, 375354
• CPC Class Codes: G01R 19/0084 measuring voltage only all subgroups of G01R19/00 take precedence
• CPC Class Codes: G05F 1/56 using semiconductor devices in series with the load as final control devices G05F1/461 takes precedence
• CPC Class Codes: G05F 1/575 characterised by the feedback circuit
• CPC Class Codes: G06F 1/06 Clock generators producing several clock signals G06F1/08 - G06F1/14 take precedence
• CPC Class Codes: G06F 1/12 Synchronisation of different clock signals provided by a plurality of clock generators
• CPC Class Codes: G06F 1/3237 by disabling clock generation or distribution
• CPC Class Codes: G06F 1/3287 by switching off individual functional units in the computer system
• CPC Class Codes: G06F 1/3296 by lowering the supply or operating voltage
• CPC Class Codes: G06F 11/3041 where the computing system component is an input/output interface interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units G06F13/00
• CPC Class Codes: G06F 11/3414 Workload generation, e.g. scripts, playback
• CPC Class Codes: G06F 13/102 where the programme performs an interfacing function, e.g. device driver G06F13/105 takes precedence; scheduling within device drivers G06F9/52; contention policies within device drivers G06F9/4881
• CPC Class Codes: H02M 1/0045 Converters combining the concepts of switch-mode regulation and linear regulation, e.g. linear pre-regulator to switching converter, linear and switching converter in parallel, same converter or same transistor operating either in linear or switching mode
• CPC Class Codes: H02M 3/158 including plural semiconductor devices as final control devices for a single load
• CPC Class Codes: H03K 17/687 the devices being field-effect transistors
• CPC Class Codes: H03L 7/00 Automatic control of frequency or phase; Synchronisation
• CPC Class Codes: H03L 7/06 using a reference signal applied to a frequency- or phase-locked loop
• CPC Class Codes: H03L 7/18 using a frequency divider or counter in the loop H03L7/20, H03L7/22 take precedence
• CPC Class Codes: H03L 7/181 a numerical count result being used for locking the loop, the counter counting during fixed time intervals H03L7/1806 takes precedence
• CPC Class Codes: H03M 1/12 Analogue/digital converters H03M1/001 – H03M1/10 take precedence
• CPC Class Codes: Y02B 70/10 Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
• CPC Class Codes: Y02D 10/00 : Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A clock synchronizer adapted to synchronize reading a Timer that is clocked asynchronously to the system clock.

Claims

1. An apparatus comprising:

an internal clock coupled to a synchronizer facility;

an enable coupled to said synchronizer facility;

a synchronous clock coupled to said synchronizer facility;

said synchronizer facility coupled to a timer;

said synchronizer facility being adapted to output a first synchronized clock as a function of said internal clock, said synchronous clock, and said enable; and

said timer being adapted to count as a function of said first synchronized clock; and

wherein said synchronizer facility is further characterized as comprising;

a first flip-flop adapted to;

receive said internal clock;

receive said synchronous clock;

receive said enable;

output a second synchronized clock as a function of said internal clock and said synchronous clock if said enable is de-asserted; and

output said second synchronized clock as a function of said internal clock and said enable if said enable is asserted;

a second flip-flop adapted to;

receive said second synchronized clock;

receive said synchronous clock;

receive said internal clock;

receive said enable;

output a third synchronized clock as a function of said second synchronized clock and said synchronous clock if said enable is de-asserted; and

output said third synchronized clock as a function of said internal clock and said enable if said enable is asserted; and

a first gating circuit adapted to output said first synchronized clock as a function of said third synchronized clock and said internal clock.

2. The clock synchronization facility of claim 1 wherein said internal clock is asynchronous to said synchronous clock.

3. The clock synchronization facility of claim 2 where said enable is asynchronous to said internal clock.

4. A method comprising:

receiving an internal clock;

receiving an enable;

receiving a synchronous clock;

developing a first synchronized clock as a function of said internal clock, said synchronous clock, and said enable; and

counting as a function of said first synchronized clock; and

wherein said developing step is further characterized as comprising the steps of;

selectively storing said internal clock as a function of;

said synchronous clock if said enable is de-asserted; and

said enable if said enable is asserted;

outputting a second synchronized clock as a function of said selectively stored internal clock;

selectively storing said second synchronized clock as a function of

said synchronous clock if said enable is de-asserted; and

said enable if said enable is asserted;

outputting a third synchronized clock as a function of said selectively stored second synchronized clock; and

developing said first synchronized clock as a function of said third synchronized clock and said internal clock.

5. The method of claim 4 wherein said internal clock is asynchronous to said synchronous clock.

6. The method of claim 5 wherein said enable is asynchronous to said internal clock.

7. A clock synchronization facility configured to perform the steps of a method according to any one of claims 4 to 6.

8. A non-transitory computer readable medium including executable instructions which, when executed in a processing system, causes the processing system to perform the steps of a method according to any one of claims 4 to 6.