Solving unstable universal asynchronous receive transmit (UART) communication between a power manager and a universal serial bus (USB)-bridge device

• US 9,772,650 B2
• Filed: 12/29/2015
• Issued: 09/26/2017
• Est. Priority Date: 12/29/2015
• Status: Expired due to Fees

• Current Assignee: Western Digital Technologies Incorporated (Western Digital Corporation)
• Original Assignee: Western Digital Technologies Incorporated (Western Digital Corporation)
• Inventors: Nguyen, Mark, Neumann, Charles A.
• Primary Examiner(s): Stoynov, Stefan
• Application Number:
  US14/983,221
• Publication Number:
  US 20170185100A1
• Time in Patent Office: 637 Days
• CPC Class Codes: G06F 1/3206 Monitoring of events, devices or parameters that trigger a change in power modality
• CPC Class Codes: G06F 13/16 for access to memory bus G06F13/28 takes precedence
• CPC Class Codes: G06F 13/382 using universal interface adapter
• CPC Class Codes: G06F 13/4027 using bus bridges G06F13/4022 takes precedence
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A device may comprise data storage, a power manager and a bridge device that is coupled to the data storage and to the power manager, and configured to bridge between at least a first data protocol and at least a second data protocol. The bridge device may comprise a UART, a first clock, a second clock and bridge device firmware configured to cause the bridge device to selectively configure the UART for communication using the first clock or the second clock. The power manager may be configured to, when a command is to be issued to the data storage when the bridge device firmware has configured the UART for communication using the first clock, assert a signal that causes the bridge device firmware to stop configuring the UART for communication using the first clock and to configure the UART for communication using the second clock.

Claims

1. A device, comprising:

a data storage device;

a power manager device; and

a bridge device coupled to the data storage device and to the power manager device, configured to bridge between at least a first data protocol and at least a second data protocol, the bridge device comprising;

a Universal Asynchronous Receive Transmit (UART);

a first clock;

a second clock; and

bridge device firmware configured to cause the bridge device to selectively configure the UART for communication using one of the first clock and the second clock,

wherein the power manager device is configured, when a command is to be issued to the data storage device when the bridge device firmware has configured the UART for communication using the first clock, to assert a signal that causes the bridge device firmware to stop configuring the UART for communication using the first clock and to configure the UART for communication using the second clock.

2. The device of claim 1, wherein the bridge device further comprises a plurality of General Purpose Input Output (GPIO) ports and wherein the power manager device is configured to assert the signal on a selected one of the plurality of GPIO ports.

3. The device of claim 1, wherein the first clock comprises a ring oscillator.

4. The device of claim 1, wherein the second clock comprises a Phase Locked Loop (PLL) oscillator.

5. The device of claim 1, wherein the bridge device is configured to configure the UART for communication using the first clock responsive to the bridge device being in a first mode.

6. The device of claim 5, wherein the first mode includes a low power mode.

7. The device of claim 1, wherein the bridge device is configured to configure the UART for communication using the second clock responsive to the bridge device being in a second mode.

8. The device of claim 7, wherein the second mode includes a normal operation power mode.

9. The device of claim 1, wherein the power manager device is further configured to assert the signal upon occurrence of a selected event.

10. The device of claim 9, wherein the selected event comprises at least one of an issued command, a data storage device-related event, a cable plug or unplug-related event and a button press-related event.

11. The device of claim 1, wherein the power manager device is further configured to send to the bridge device, after the UART has been configured for communication using the second clock, at least one of a notification signal, one or more commands, and an end of notification signal.

12. A method, comprising:

providing a device comprising a data storage device and a bridge device coupled to the data storage device, the bridge device comprising;

a Universal Asynchronous Receive Transmit (UART);

a first clock; and

a second clock, the bridge device being configured to bridge between at least a first data protocol and at least a second data protocol;

selectively configuring the UART for communication using one of the first clock and the second clock; and

responsive to the determining that the UART is configured for communication using the first clock and the determining that a command is to be issued to the data storage device, asserting a signal configured to disable communications with the UART using the first clock and to enable communications with the UART using the second clock.

13. The method of claim 12, wherein the bridge device further comprises a plurality of General Purpose Input Output (GPIO) ports and wherein asserting the signal comprises asserting a signal on a selected one of the plurality of GPIO ports.

14. The method of claim 12, wherein providing is performed with the first clock comprising a ring oscillator.

15. The method of claim 12, wherein providing is performed with the second clock comprising a Phase Locked Loop (PLL) oscillator.

16. The method of claim 12, wherein selectively configuring comprises configuring the UART for communication using the first clock responsive to the bridge device being in a first mode.

17. The method of claim 16, wherein the first mode includes a low power mode.

18. The method of claim 12, wherein selectively configuring comprises configuring the UART for communication using the second clock responsive to the bridge device being in a second mode.

19. The method of claim 18, wherein the second mode includes a normal operation power mode.

20. The method of claim 12, wherein asserting the signal is further performed upon occurrence of a selected event.

21. The method of claim 20, wherein the selected event comprises at least one of an issued command, a data storage device-related event, a cable plug or unplug-related event and a button press-related event.

22. The method of claim 12, further comprising sending to the bridge device, after the UART has been configured for communication using the second clock, at least one of a notification signal, one or more commands, and an end of notification signal.

23. A circuit board, comprising:

a power manager device; and

a bridge device configured to couple to the power manager device, the bridge device being configured to couple to a data storage device and to bridge between at least a first data protocol and at least a second data protocol, the bridge device comprising;

a Universal Asynchronous Receive Transmit (UART);

a first clock;

a second clock; and

bridge device firmware configured to cause the bridge device to selectively configure the UART for communication using one of the first clock and the second clock,

wherein the power manager device is configured to, when a command is to be issued to the data storage device when the bridge device firmware has configured the UART for communication using the first clock, assert a signal that causes the bridge device firmware to stop configuring the UART for communication using the first clock and to instead configure the UART for communication using the second clock.