Power shutdown with isolation logic in I/O power domain
First Claim
1. An integrated circuit comprising:
- a physical layer (PHY) logic, wherein the PHY logic is powered by a first power domain; and
at least one input/output (I/O) cell in communication with the PHY logic, wherein the at least one I/O cell houses an I/O logic, an isolation control logic, a level shifter in between the I/O and isolation control logics, and an I/O buffer, wherein the at least one I/O cell is powered by a second power domain when the first power domain is off, and wherein the isolation control logic is in the second power domain and receives power from only the second power domain.
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Abstract
A circuit for that includes isolation logic is disclosed. In one aspect, circuit comprises at least one input/output (I/O) cell, the I/O cell further including circuitry functions, isolation control logic, and a capability to receive power to the I/O cell from a power domain source. In a second aspect an integrated circuit comprises a physical layer (PHY) logic and at least one input/output (I/O) cell in communication with the PHY logic. The I/O cell capable of receiving power from a plurality of power domains. The I/O cell includes an isolation control logic and an I/O logic capable of receiving power from one power domain of a plurality of power domains, wherein the I/O logic and the isolation controller are arranged in communication through a level shifter for shifting power to maintain an active operation of the at least one I/O cell; wherein since the isolation control logic is within the I/O cell, only one active power domain of the plurality of power domains is required.
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Citations
21 Claims
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1. An integrated circuit comprising:
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a physical layer (PHY) logic, wherein the PHY logic is powered by a first power domain; and at least one input/output (I/O) cell in communication with the PHY logic, wherein the at least one I/O cell houses an I/O logic, an isolation control logic, a level shifter in between the I/O and isolation control logics, and an I/O buffer, wherein the at least one I/O cell is powered by a second power domain when the first power domain is off, and wherein the isolation control logic is in the second power domain and receives power from only the second power domain. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A method comprising:
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powering a physical layer (PHY) logic a first power domain, the PHY logic in communication with at least one input/output (I/O) cell, the at least one I/O cell housing an I/O logic, an isolation control logic, a level shifter in between the I/O and isolation control logics, and an I/O buffer; and powering the at least one I/O cell by a second power domain when the first power domain is off, such the isolation control logic is in the second power domain and receives power from only the second power domain. - View Dependent Claims (11, 12, 13, 14, 15, 16, 17, 18)
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19. An integrated circuit comprising:
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a physical layer (PHY) logic, wherein the PHY logic is powered by a first power domain; and at least one input/output (I/O) cell in communication with the PHY logic, wherein the at least one I/O cell houses an I/O logic, an isolation control logic, a level shifter in between the I/O and isolation control logics, and an I/O buffer, wherein the at least one I/O cell is powered by a second power domain when the first power domain is off, wherein the isolation control logic is in the second power domain, wherein the first power domain is a core logic power domain, and wherein the second power domain is an I/O power domain. - View Dependent Claims (20, 21)
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Specification