Power shutdown with isolation logic in I/O power domain

• US 9,772,668 B1
• Filed: 09/27/2012
• Issued: 09/26/2017
• Est. Priority Date: 09/27/2012
• Status: Active Grant

• Current Assignee: Cadence Design Systems Incorporated (Cadence Group)
• Original Assignee: Cadence Design Systems Incorporated (Cadence Group)
• Inventors: Soebroto, Tobing, DeMaris, James, Medero, Jose L., Tucker, Scott J.
• Primary Examiner(s): Cassity, Robert
• Application Number:
  US13/629,424
• Time in Patent Office: 1,825 Days
• Field of Search: 713300
• CPC Class Codes: G06F 1/26 Power supply means, e.g. regulation thereof for memories G11C
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/3287 by switching off individual functional units in the computer system
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A circuit for that includes isolation logic is disclosed. In one aspect, circuit comprises at least one input/output (I/O) cell, the I/O cell further including circuitry functions, isolation control logic, and a capability to receive power to the I/O cell from a power domain source. In a second aspect an integrated circuit comprises a physical layer (PHY) logic and at least one input/output (I/O) cell in communication with the PHY logic. The I/O cell capable of receiving power from a plurality of power domains. The I/O cell includes an isolation control logic and an I/O logic capable of receiving power from one power domain of a plurality of power domains, wherein the I/O logic and the isolation controller are arranged in communication through a level shifter for shifting power to maintain an active operation of the at least one I/O cell; wherein since the isolation control logic is within the I/O cell, only one active power domain of the plurality of power domains is required.

Claims

1. An integrated circuit comprising:

a physical layer (PHY) logic, wherein the PHY logic is powered by a first power domain; and

at least one input/output (I/O) cell in communication with the PHY logic, wherein the at least one I/O cell houses an I/O logic, an isolation control logic, a level shifter in between the I/O and isolation control logics, and an I/O buffer, wherein the at least one I/O cell is powered by a second power domain when the first power domain is off, and wherein the isolation control logic is in the second power domain and receives power from only the second power domain.

2. The integrated circuit of claim 1, wherein the isolation control logic is in communication with the PHY logic external to the at least one I/O cell, further wherein the second power domain provides power to the isolation control logic and circuitry functions of the at least one I/O cell.

3. The integrated circuit of claim 2, wherein the first power domain is a core logic power domain and the second power domain is an I/O power domain.

4. The integrated circuit of claim 2, wherein the I/O logic is capable of receiving power from both the first and the second power domains.

5. The integrated circuit of claim 1, wherein the first power domain comprises any of a core power domain and a protocol power domain.

6. The integrated circuit of claim 1, wherein the at least one I/O cell comprises a plurality of I/O cells.

7. The integrated circuit of claim 1, wherein the circuit is any of a system on a chip (SoC), processor, chip, network on a chip (NaC), and integrated circuit (IC).

8. The integrated circuit of claim 1, wherein the integrated circuit is in any of a power shut-off operation (PSO) and a low power operation state.

9. The integrated circuit of claim 1, wherein the first power domain is of a voltage between 0.5 v and 5.0 v.

10. A method comprising:

powering a physical layer (PHY) logic a first power domain, the PHY logic in communication with at least one input/output (I/O) cell, the at least one I/O cell housing an I/O logic, an isolation control logic, a level shifter in between the I/O and isolation control logics, and an I/O buffer; and

powering the at least one I/O cell by a second power domain when the first power domain is off, such the isolation control logic is in the second power domain and receives power from only the second power domain.

11. The method of claim 10, wherein the isolation control logic is in communication with the PHY logic external to the at least one I/O cell, further wherein the second power domain provides power to the isolation control logic and circuitry functions of the at least one I/O cell.

12. The method of claim 11, wherein the first power domain is a core logic power domain and the second power domain is an I/O power domain.

13. The method of claim 11, wherein the I/O logic is capable of receiving power from both the first and the second power domains.

14. The method of claim 10, wherein the first power domain comprises any of a core power domain and a protocol power domain.

15. The method of claim 10, wherein the at least one I/O cell comprises a plurality of I/O cells.

16. The method of claim 10, wherein an integrated circuit comprises the PHY logic and the at least one I/O cell, and the integrated circuit is any of a system on a chip (SoC), processor, chip, network on a chip (NaC), and integrated circuit (IC).

17. The method of claim 10, wherein an integrated circuit comprises the PHY logic and the at least one I/O cell, and the integrated circuit is in any of a power shut-off operation (PSO) and a low power operation state.

18. The method of claim 10, wherein the first power domain is of a voltage between 0.5 v and 5.0 v.

19. An integrated circuit comprising:

a physical layer (PHY) logic, wherein the PHY logic is powered by a first power domain; and

at least one input/output (I/O) cell in communication with the PHY logic, wherein the at least one I/O cell houses an I/O logic, an isolation control logic, a level shifter in between the I/O and isolation control logics, and an I/O buffer, wherein the at least one I/O cell is powered by a second power domain when the first power domain is off, wherein the isolation control logic is in the second power domain, wherein the first power domain is a core logic power domain, and wherein the second power domain is an I/O power domain.

20. The integrated circuit of claim 19, wherein the isolation control logic is in communication with the PHY logic external to the at least one I/O cell, further wherein the second power domain provides power to the isolation control logic and circuitry functions of the at least one I/O cell.

21. The integrated circuit of claim 19, wherein the I/O logic is capable of receiving power from both the first and the second power domains.