Capacitive discharge circuit for touch sensitive screen

• US 9,772,726 B2
• Filed: 11/03/2014
• Issued: 09/26/2017
• Est. Priority Date: 11/03/2014
• Status: Active Grant

• Current Assignee: STMicroelectronics International N.V. (STMicroelectronics NV)
• Original Assignee: STMicroelectronics Asia Pacific Pte Limited (STMicroelectronics NV)
• Inventors: Cheong, Chee Weng, Guo, Dianbo, Tan, Kien Beng, Guedon, Yannick
• Primary Examiner(s): SHAH, PRIYANK J
• Application Number:
  US14/531,631
• Publication Number:
  US 20160124541A1
• Time in Patent Office: 1,058 Days
• CPC Class Codes: G06F 3/041 Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
• CPC Class Codes: G06F 3/0418 for error correction or compensation, e.g. based on parallax, calibration or alignment
• CPC Class Codes: G06F 3/044 by capacitive means
• CPC Class Codes: G06F 3/0446 using a grid-like structure of electrodes in at least two directions, e.g. using row and column electrodes

Abstract

A capacitive discharge circuit includes a line having a capacitance, a switched capacitor circuit including a capacitor, a switched circuit coupled to the line, and a voltage regulator coupled between the switched capacitor circuit and the switched circuit. A controller operates the switched capacitor circuit and switched circuit to in a first phase, charge the capacitor by coupling the capacitor between a common mode and a power supply, and in a second phase, discharge the capacitor by coupling the voltage regulator in series with the capacitor between the power supply node a ground. The controller is also configured to in a third phase, charge the capacitor by coupling the capacitor between the common mode and the power supply, and in a fourth phase, share charge between the line and the capacitor by coupling the voltage regulator and the capacitor in series between the line and the ground.

Claims

1. A capacitive discharge circuit comprising:

a line having a capacitance associated therewith;

a switched capacitor circuit comprising a capacitor;

a switched circuit coupled to the line;

a voltage regulator circuit coupled between the switched capacitor circuit and the switched circuit; and

a controller configured to operate the switched capacitor circuit and the switched circuit so as to;

in a first phase, charge the capacitor by coupling the capacitor between a common mode node and a power supply node,

in a second phase, discharge the capacitor by coupling the voltage regulator circuit in series with the capacitor between the power supply node and a ground node,

in a third phase, charge the capacitor by coupling the capacitor between the common mode node and the power supply node, and

in a fourth phase, share charge between the line and the capacitor by coupling the voltage regulator circuit and the capacitor in series between the line and the ground node.

2. The capacitive discharge circuit of claim 1, wherein the controller, before performing the third and fourth phases, is configured to repeat the first and second phases if an output of the voltage regulator circuit is less than a regulator threshold voltage.

3. The capacitive discharge circuit of claim 1, wherein the controller is configured to repeat the first and second phases a plurality of times before proceeding to the third phase.

4. The capacitive discharge circuit of claim 1, wherein the controller is configured to repeat the third and fourth phases until a voltage on the line is less than a line threshold voltage.

5. The capacitive discharge circuit of claim 1, wherein the controller is configured to repeat the third and fourth phases at least twice.

6. The capacitive discharge circuit of claim 1, wherein the voltage regulator circuit includes an input coupled to the common mode node and is configured to output a regulator voltage that is at most equal to a regulator threshold voltage.

7. The capacitive discharge circuit of claim 1, wherein the voltage regulator circuit comprises:

an operational amplifier having a first input coupled to the common mode node, a second input coupled to the switched capacitor circuit, and an output;

a transistor having a first conduction terminal coupled to the switched circuit, a second conduction terminal coupled to the switched capacitor circuit, and a control terminal coupled to the output of the operational amplifier.

8. The capacitive discharge circuit of claim 1, wherein the switched circuit comprises a switch circuit having inputs coupled to the line and to the power supply node, and an output coupled to the voltage regulator circuit.

9. The capacitive discharge circuit of claim 1, wherein the switched capacitor circuit comprises:

a first switch circuit having inputs coupled to the voltage regulator circuit and to the common mode node, and an output coupled to a first terminal of the capacitor; and

a second switch circuit having inputs coupled to the power supply node and to the ground node, and an output coupled to a second terminal of the capacitor.

10. A method of discharging a capacitance on a line comprising:

in a first phase, charge a capacitor by coupling the capacitor between a common mode node and a power supply node,

in a second phase, discharge the capacitor by coupling a voltage regulator circuit in series with the capacitor between the power supply node and a ground node,

in a third phase, charge the capacitor by coupling the capacitor between the common mode node and the power supply node, and

in a fourth phase, share charge between the line and the capacitor by coupling the voltage regulator circuit and capacitor in series between the line and the ground node.

11. The method of claim 10, further comprising before performing the third and fourth phases, repeating the first and second phases if an output of the voltage regulator is less than a regulator threshold voltage.

12. The method of claim 10, further comprising repeating the first and second phases a plurality of times before proceed to the third phase.

13. The method of claim 10, further comprising repeating the third and fourth phases until a voltage on the line is less than a line threshold voltage.

14. The method of claim 10, further comprising repeating the third and fourth phases at least twice.