Interrupt management system for deferring low priority interrupts in real-time system

• US 9,772,963 B2
• Filed: 07/26/2015
• Issued: 09/26/2017
• Est. Priority Date: 07/26/2015
• Status: Active Grant

• Current Assignee: NXP USA, Inc. (NXP Semiconductors NV)
• Original Assignee: NXP USA, Inc. (NXP Semiconductors NV)
• Inventors: Jain, Priyanka, Agrawal, Girraj K., Srivastava, Rajan
• Primary Examiner(s): Shyu, Jing-Yih
• Application Number:
  US14/809,269
• Publication Number:
  US 20170024342A1
• Time in Patent Office: 793 Days
• CPC Class Codes: G06F 13/32 using combination of interrupt and burst mode transfer
• CPC Class Codes: G06F 9/4825 Interrupt from clock, e.g. time of day
• CPC Class Codes: G06F 9/4837 time dependent

Abstract

An interrupt management system for managing multiple interrupts includes a timer and an interrupt management sub-system. The interrupt management sub-system receives first and second interrupts, determines the first interrupt to be a real-time interrupt and the second interrupt to be a non-real-time interrupt, initializes the timer for a predetermined time period on reception of the first interrupt, and determines whether the second interrupt is either a maskable or non-maskable interrupt. The interrupt management sub-system transmits the first interrupt to an interrupt controller, en-queues the second interrupt during the predetermined time period, and transmits the second interrupt to the interrupt controller after the predetermined time period when the second interrupt is a maskable interrupt. The interrupt management sub-system transmits the second interrupt to the interrupt controller during the predetermined time period when the second interrupt is a non-maskable interrupt.

Claims

1. An interrupt management system connected to an interrupt controller for managing a plurality of interrupts, the interrupt management system comprising:

a timer; and

an interrupt management sub-system, connected to the timer, and including first and second interrupt status registers, wherein the interrupt management sub-system is configured for;

receiving the plurality of interrupts,

determining a first interrupt of the plurality of interrupts to be a real-time interrupt and storing a first status value therefor in the first interrupt status register,

determining a second interrupt of the plurality of interrupts to be a non-real-time interrupt and storing a second status value therefor in the first interrupt status register,

determining the second interrupt to be at least one of a maskable interrupt and a non-maskable interrupt based on the second status value,

determining a third interrupt of the plurality of interrupts to be one of a real-time interrupt and a non-real-time interrupt and storing a third status value therefor in the second interrupt status register,

determining a fourth interrupt of the plurality of interrupts to be one of a real-time interrupt and a non-real-time interrupt and storing a fourth status value therefor in the second interrupt status register,

initializing the timer for a predetermined time period based on the first interrupt, wherein the timer generates a timer window active signal after the predetermined time period,

transmitting the first interrupt to the interrupt controller,

queuing the second interrupt during the predetermined time period when the second interrupt is a maskable interrupt, and

transmitting the second interrupt to the interrupt controller when the second interrupt is a non-maskable interrupt.

2. The interrupt management system of claim 1, wherein the interrupt management sub-system is further configured for transmitting the second interrupt to the interrupt controller after the predetermined time period based on the timer window active signal when the second interrupt is a maskable interrupt.

3. The interrupt management system of claim 1, wherein the interrupt management sub-system is further configured for receiving a timer window abort signal and transmitting the plurality of interrupts to the interrupt controller after receiving the timer window abort signal.

4. The interrupt management system of claim 3, wherein the timer generates a programmed timer value indicative of the predetermined time period.

5. The interrupt management system of claim 1, further comprising a first set of timers, including the timer, connected to the interrupt management sub-system.

6. The interrupt management system of claim 5, wherein the interrupt management sub-system is further configured for:

determining a first set of interrupts of the plurality of interrupts, including the first interrupt, to be real-time interrupts, and

initializing the first set of timers based on the first set of interrupts, wherein each timer of the first set of timers corresponds to at least one real-time interrupt of the first set of interrupts.

7. The interrupt management system of claim 6, wherein each timer generates a corresponding timer window active signal after a corresponding predetermined time period.

8. A system for managing a plurality of interrupts, wherein the plurality of interrupts includes first and second interrupts, the system comprising:

a timer for receiving a first interrupt signal corresponding to the first interrupt and generating a timer window active signal after a predetermined time period;

a first interrupt status register for storing first and second status values, and providing first and second status signals, respectively, wherein a first logic state of the first status signal indicates that the first interrupt is a maskable interrupt and a second logic state of the first status signal indicates that the first interrupt is a non-maskable interrupt, a first logic state of the second status signal indicates that the second interrupt is a maskable interrupt, and a second logic state of the second status signal indicates that the second interrupt is a non-maskable interrupt;

a second interrupt status register that stores third and fourth status values and provides third and fourth status signals, respectively, wherein a first logic state of the third status signal indicates that the first interrupt signal is a real-time interrupt, and a second logic state of the third status signal indicates that the first interrupt signal is a non-real-time interrupt, and wherein a first logic state of the fourth status signal indicates that the second interrupt signal is a real-time interrupt, and a second logic state of the fourth status signal indicates that the second interrupt signal is a non-real-time interrupt;

a first logic gate having a first input terminal connected to the timer for receiving the timer window active signal, a second input terminal connected to the first interrupt status register for receiving the first status signal, a third input terminal for receiving a timer window abort signal, and an output terminal for generating a first interrupt enable signal;

a second logic gate having a first input terminal connected to the timer for receiving the timer window active signal, a second input terminal connected to the first interrupt status register for receiving the second status signal, a third input terminal for receiving the timer window abort signal, and an output terminal for generating a second interrupt enable signal;

a third logic gate having a first input terminal for receiving the first interrupt signal, a second input terminal connected to the output terminal of the first logic gate for receiving the first interrupt enable signal, and an output terminal for generating a first transmission signal;

a fourth logic gate having a first input terminal for receiving a second interrupt signal corresponding to the second interrupt, a second input terminal connected to the output terminal of the second logic gate for receiving the second interrupt enable signal, and an output terminal for generating a second transmission signal; and

an interrupt controller connected to the third and fourth logic gates for receiving the first and second transmission signals, respectively, and generating first and second interrupt transmission signals, respectively.

9. The system of claim 8, wherein each of the first and second logic gates further includes a fourth input terminal connected to the second interrupt status register for receiving the third and fourth status signals, respectively.

10. The system of claim 9, wherein the timer generates the timer window active signal at a first logic state during the predetermined time period and at a second logic state after the predetermined time period.

11. The system of claim 9, further comprising:

a first buffer for receiving, storing, and transmitting the first interrupt signal, wherein the first input terminal of the third logic gate is connected to the first buffer for receiving the first interrupt signal; and

a second buffer for receiving, storing, and transmitting the second interrupt signal, wherein the first input terminal of the fourth logic gate is connected to the second buffer for receiving the second interrupt signal.