Integrated bit-line airgap formation and gate stack post clean

• US 9,773,695 B2
• Filed: 10/24/2016
• Issued: 09/26/2017
• Est. Priority Date: 07/31/2014
• Status: Active Grant

• Current Assignee: Applied Materials Incorporated
• Original Assignee: Applied Materials Incorporated
• Inventors: Purayath, Vinod R., Thakur, Randhir, Venkataraman, Shankar, Ingle, Nitin K.
• Primary Examiner(s): Rizkallah, Kimberly
• Assistant Examiner(s): Jang, Bo Bin
• Application Number:
  US15/332,910
• Publication Number:
  US 20170040207A1
• Time in Patent Office: 337 Days
• Field of Search: 438400, 438421, 438422
• CPC Class Codes: H01J 37/32357 Generation remote from the workpiece, e.g. down-stream
• CPC Class Codes: H01L 21/02071 the processing being a delineation, e.g. RIE, of conductive layers
• CPC Class Codes: H01L 21/31116 by dry-etching
• CPC Class Codes: H01L 21/67069 for drying etching
• CPC Class Codes: H01L 21/67103 mainly by conduction
• CPC Class Codes: H01L 21/68764 characterised by a movable susceptor, stage or support, others than those only rotating on their own vertical axis, e.g. susceptors on a rotating caroussel
• CPC Class Codes: H01L 21/764 Air gaps H01L21/76264 takes precedence
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/40114 the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
• CPC Class Codes: H01L 29/40117 the electrodes comprising a charge-trapping insulator
• CPC Class Codes: H01L 29/66833 with a charge trapping gate insulator, e.g. MNOS transistors
• CPC Class Codes: H01L 29/7887 Programmable transistors with more than two possible different levels of programmation
• CPC Class Codes: H10B 43/30 characterised by the memory core region

Abstract

Methods of forming flash memory cells are described which incorporate air gaps for improved performance. The methods are useful for so-called “2-d flat cell” flash architectures. 2-d flat cell flash memory involves a reactive ion etch to dig trenches into multi-layers containing high work function and other metal layers. The methods described herein remove the metal oxide debris from the sidewalls of the multi-layer trench and then, without breaking vacuum, selectively remove shallow trench isolation (STI) oxidation which become the air gaps. Both the metal oxide removal and the STI oxidation removal are carried out in the same mainframe with highly selective etch processes using remotely excited fluorine plasma effluents.

Claims

1. A method of forming a flash device, the method comprising:

transferring a patterned substrate into a substrate processing mainframe, wherein the patterned substrate comprises a stack of materials including a control gate layer over a block layer over a charge trap layer over a protective liner over a polysilicon layer, and wherein a trench has been etched through each layer and a sidewall of the trench has metal-oxide residue left over from a reactive-ion etch process used to create the trench;

transferring the patterned substrate into a first substrate processing chamber mounted on the substrate processing mainframe;

forming first plasma effluents by flowing a first fluorine-containing precursor into a first remote plasma region within the first substrate processing chamber while striking a plasma;

flowing the first plasma effluents through a showerhead into a substrate processing region housing the patterned substrate within the first substrate processing chamber;

forming a pocket for an air gap between two adjacent polysilicon gates by reacting the first plasma effluents with a shallow trench isolation silicon oxide disposed between the two adjacent polysilicon gates, wherein reacting the first plasma effluents with the shallow trench isolation silicon oxide selectively removes a portion of the shallow trench isolation silicon oxide;

forming second plasma effluents by flowing a second fluorine-containing precursor into the first remote plasma region while striking a plasma;

selectively removing the metal-oxide residue from the sidewall of the trench by flowing the second plasma effluents into the substrate processing region housing the patterned substrate and reacting the second plasma effluents with the metal-oxide residue; and

removing the patterned substrate from the substrate processing mainframe, wherein the patterned substrate is not exposed to atmosphere between transferring the patterned substrate into the substrate processing mainframe and removing the patterned substrate from the substrate processing mainframe.

2. The method of forming a flash device of claim 1, wherein an electron temperature in the substrate processing region during reacting the first plasma effluents and reacting the second plasma effluents is below 0.5 eV.

3. The method of forming a flash device of claim 1, wherein the metal-oxide residue comprises at least one of one of tungsten, hafnium, zirconium, tantalum, titanium, aluminum, ruthenium, palladium, rhodium, gold, cobalt, beryllium, iridium or platinum according to embodiments.

4. The method of forming a flash device of claim 1, wherein a work function of the charge trap layer is greater than or about 4.8 eV.

5. The method of forming a flash device of claim 1, wherein the control gate layer comprises tungsten.

6. A method of forming a flash device, the method comprising:

transferring a patterned substrate into a substrate processing mainframe, wherein the patterned substrate comprises a stack of materials including a block layer over a charge trap layer over a protective liner over a polysilicon layer, and wherein a trench has been etched through each layer and a sidewall of the trench has metal-oxide residue left over from a reactive-ion etch process used to create the trench;

transferring the patterned substrate into a first substrate processing chamber mounted on the substrate processing mainframe;

forming first plasma effluents by flowing a first fluorine-containing precursor into a first remote plasma region within the first substrate processing chamber while striking a plasma;

flowing the first plasma effluents through a showerhead into a first substrate processing region housing the patterned substrate within the first substrate processing chamber;

forming a pocket for an air gap between two adjacent polysilicon gates by selectively removing a portion of a shallow trench isolation silicon oxide disposed between the two adjacent polysilicon gates;

wherein selectively removing a portion of the shallow trench isolation silicon oxide comprises reacting the first plasma effluents with the shallow trench isolation silicon oxide;

transferring the patterned substrate from the first substrate processing chamber to a second substrate processing chamber mounted on the substrate processing mainframe;

forming second plasma effluents by flowing a second fluorine-containing precursor into a second remote plasma region within the second substrate processing chamber while striking a plasma;

flowing the second plasma effluents into a second substrate processing region within the second substrate processing chamber;

wherein the second substrate processing region houses the patterned substrate; and

selectively removing the metal-oxide residue from the sidewall of the trench by reacting the second plasma effluents with the metal-oxide residue.

7. The method of forming a flash device of claim 6, wherein the flash device has a 2-d flat cell architecture.

8. The method of forming a flash device of claim 6, wherein flowing the first fluorine-containing precursor into a first remote plasma region further comprises flowing a precursor having an OH group directly into the first substrate processing region without first passing the precursor having an OH group in any plasma.

9. The method of forming a flash device of claim 6, wherein flowing the first fluorine-containing precursor into a first remote plasma region further comprises flowing NxHy [x and y are >

=1] directly into the first substrate processing region without first exciting the NxHy in any plasma.

10. The method of forming a flash device of claim 6, wherein the protective liner is a nitridation layer or a silicon nitride layer.

11. The method of forming a flash device of claim 6, wherein the trench has a width less than or about 15 nm.

12. The method of forming a flash device of claim 6, wherein the block layer comprises hafnium oxide.

13. The method of forming a flash device of claim 6, wherein flowing the first fluorine-containing precursor into a first remote plasma region further comprises flowing one of an oxygen-containing precursor or a hydrogen-containing precursor into the first remote plasma region.

14. The method of forming a flash device of claim 6, wherein the first fluorine-containing precursor comprises nitrogen trifluoride.

15. The method of forming a flash device of claim 6, wherein the second fluorine-containing precursor comprises nitrogen trifluoride.