Devices and methods of forming VFET with self-aligned replacement metal gates aligned to top spacer post top source drain EPI

• US 9,773,708 B1
• Filed: 08/24/2016
• Issued: 09/26/2017
• Est. Priority Date: 08/24/2016
• Status: Expired due to Fees

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: GlobalFoundries, Inc.
• Inventors: Zhang, John, Bentley, Steven, Lim, Kwan-Yong
• Primary Examiner(s): Pham, Thanh V
• Application Number:
  US15/245,634
• Time in Patent Office: 398 Days
• CPC Class Codes: H01L 21/823828 with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
• CPC Class Codes: H01L 21/823878 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 21/823885 with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface with a current flow parallel to the substrate surface H01L21/823821
• CPC Class Codes: H01L 27/092 complementary MIS field-effect transistors
• CPC Class Codes: H01L 29/42392 fully surrounding the channel, e.g. gate-all-around
• CPC Class Codes: H01L 29/4966 the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2 H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66666 Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence
• CPC Class Codes: H01L 29/78618 characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure silicide contacts, electrodes in general H01L29/458
• CPC Class Codes: H01L 29/78642 Vertical transistors
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

Devices and methods of fabricating vertical field effect transistors on semiconductor devices are provided. One intermediate semiconductor includes: a substrate, a bottom spacer layer above the substrate, a plurality of fins, wherein at least one fin is an n-fin and at least one fin is a p-fin; a high-k layer and a work function metal over the bottom spacer layer and around the plurality of fins; a top spacer above the high-k layer and the work function metal and surrounding a top area of the fins; a top source/drain structure over each fin; a dielectric capping layer over the top source/drain structure; a fill metal surrounding the work function metal; and a liner.

Claims

1. A method comprising:

obtaining an intermediate semiconductor device having a substrate, a bottom spacer layer above the substrate, a plurality of fins, wherein at least one fin is an n-fin and at least one fin is a p-fin, and a set of vertical hardmasks disposed over each fin;

depositing a sacrificial dielectric layer and a thin sacrificial gate layer over the plurality of fins and the bottom spacer layer;

depositing an interlayer dielectric material between the plurality of fins and planarizing a top surface of the intermediate semiconductor device to a top surface of the set of vertical hardmasks;

forming a top spacer in the interlayer dielectric material surrounding a top surface of the fins;

providing a semiconductor material over each fin to form a top source/drain structure;

depositing a dielectric capping layer over the top source/drain structure;

removing the interlayer dielectric material, the sacrificial dielectric layer, and the thin sacrificial gate layer, and depositing a high-k layer adjacent the plurality of fins, a work function metal, and a fill metal between the fins; and

recessing the fill metal between the plurality of fins and depositing a liner.

2. The method of claim 1, further comprising:

providing a shallow trench isolation region between at least some of the fins.

3. The method of claim 1, further comprising:

providing a diffusion barrier between the substrate and a metal layer and between the fins and the metal layer, the metal layer being above the substrate.

4. The method of claim 1, wherein the interlayer dielectric material comprises a flowable oxide.

5. The method of claim 1, wherein the forming a top spacer comprises:

etching a region surrounding each fin to a top surface of the fins;

depositing a top spacer in the region; and

etching above the vertical spacers.

6. The method of claim 5, wherein the etching the region comprises a dry etch.

7. The method of claim 5, wherein the top spacer comprises SiN, SiCO, SiOCN, or SiBCN.

8. The method of claim 1, further comprising:

introducing a set of dopants into the top source/drain structure.

9. The method of claim 8, wherein the set of dopants includes phosphorus over each n-fin and boron over each p-fin.

10. The method of claim 1, further comprising:

planarizing a top surface of the intermediate semiconductor device following depositing the dielectric capping layer.

11. The method of claim 1, wherein the fill metal comprises a tungsten containing metal.

12. The method of claim 1, further comprising:

stopping the recessing at the bottom spacer.

13. The method of claim 1, wherein the liner comprises SiN, SiCO, or SiBCN.

14. The intermediate semiconductor device of claim 13, further comprising:

a shallow trench isolation region between at least some of the fins.

15. The intermediate semiconductor device of claim 13, further comprising:

a diffusion barrier between the substrate and a metal layer and between the fins and the metal layer, the metal layer being above the substrate.

16. The intermediate semiconductor device of claim 13, wherein the top spacer comprises SiN, SiCO, SiOCN, or SiBCN.

17. The intermediate semiconductor device of claim 13, wherein the top source/drain structure includes phosphorus doped silicon over each n-fin and boron doped silicon over each p-fin.

18. The intermediate semiconductor device of claim 13, wherein the fill metal comprises a tungsten containing metal.

19. The intermediate semiconductor device of claim 13, wherein the liner comprises SiN, SiCO, or SiBCN.