Solid-state imaging device and method of manufacturing the device

• US 9,773,825 B2
• Filed: 12/09/2014
• Issued: 09/26/2017
• Est. Priority Date: 06/26/2012
• Status: Active Grant

• Current Assignee: Panasonic Intellectual Property Management Co., Ltd. (Panasonic Holdings Corporation)
• Original Assignee: Panasonic Intellectual Property Management Co., Ltd. (Panasonic Holdings Corporation)
• Inventors: Hirase, Junji, Matsunaga, Yoshiyuki, Sato, Yoshihiro
• Primary Examiner(s): Tobergte, Nicholas
• Application Number:
  US14/565,212
• Publication Number:
  US 20150090998A1
• Time in Patent Office: 1,022 Days
• CPC Class Codes: H01L 27/1461 characterised by the photosensitive area
• CPC Class Codes: H01L 27/14612 involving a transistor
• CPC Class Codes: H01L 27/14614 having a special gate structure
• CPC Class Codes: H01L 27/1464 Back illuminated imager structures
• CPC Class Codes: H01L 27/14641 Electronic components shared by two or more pixel-elements, e.g. one amplifier shared by two pixel elements
• CPC Class Codes: H01L 27/14645 Colour imagers
• CPC Class Codes: H01L 27/14669 Infrared imagers
• CPC Class Codes: H04N 25/65 applied to reset noise, e.g. KTC noise related to CMOS structures by techniques other than CDS
• CPC Class Codes: H04N 25/75 Circuitry for providing, modifying or processing image signals from the pixel array
• CPC Class Codes: H10K 30/65 Light-sensitive field-effect devices, e.g. phototransistors
• CPC Class Codes: Y02E 10/549 Organic PV cells
• CPC Class Codes: Y02P 70/50 Manufacturing or production processes characterised by the final manufactured product

Abstract

Each unit pixel includes a photoelectric converter formed above a semiconductor region, an amplifier transistor formed in the semiconductor region, and including a gate electrode connected to the photoelectric converter, a reset transistor configured to reset a potential of the gate electrode, and an isolation region formed in the semiconductor region between the amplifier transistor and the reset transistor to electrically isolate the amplifier transistor from the reset transistor. The amplifier transistor includes a source/drain region. The source/drain region has a single source/drain structure.

Claims

1. A solid-state imaging device comprising:

a semiconductor region of a first conductivity type;

a plurality of unit pixels; and

a peripheral circuit located in a peripheral region of the plurality of unit pixels, and including a plurality of peripheral transistors; and

an insulating film isolating the plurality of peripheral transistors from each other, wherein

each of the unit pixels includes

a photoelectric converter above the semiconductor region,

an amplifier transistor in the semiconductor region, including a gate electrode connected to the photoelectric converter,

a reset transistor in the semiconductor region, configured to reset a potential of the gate electrode of the amplifier transistor, and

an impurity diffusion layer isolating the amplifier transistor from the reset transistor.

2. The solid-state imaging device of claim 1, wherein the photoelectric converter includes a photoelectric conversion film containing an organic material.

3. The solid-state imaging device of claim 1, wherein a source/drain region of the amplifier transistor has a single source/drain structure.

4. The solid-state imaging device of claim 3, wherein the source/drain region contains impurities at a concentration lower than that of a source/drain region of each of the peripheral transistors.

5. The solid-state imaging device of claim 3, wherein

the amplifier transistor is a depletion transistor, and

a channel width of the amplifier transistor is substantially equal to a width of the source/drain region.

6. The solid-state imaging device of claim 3, wherein

the amplifier transistor is a depletion transistor, and

impurities implanted into the source/drain region are implanted into an entire lower surface of the gate electrode of the amplifier transistor.

7. The solid-state imaging device of claim 6, wherein the source/drain region contains a higher concentration of impurities at a portion being in contact with a contact than other portions.

8. The solid-state imaging device of claim 1, wherein the amplifier transistor and the reset transistor are of a p-channel type.

9. The solid-state imaging device of claim 1, wherein

ones of the plurality of peripheral transistors are of a same channel type as the transistors included in the unit pixels,

each of the ones of the plurality of peripheral transistors includes a gate electrode containing silicon, and has a dual source/drain structure of a first source/drain containing impurities at a first concentration, and a second source/drain disposed outside the first source/drain and containing impurities at a second concentration higher than the first concentration, and

the gate electrodes of the peripheral transistors having the dual source/drain structure contain impurities at a concentration equal to the second concentration.

11. The solid-state imaging device of claim 1, wherein the insulating film is disposed in the semiconductor region.

12. The solid-state imaging device of claim 1, wherein the insulating film is a shallow trench isolation (STI) region.

13. The solid-state imaging device of claim 1, wherein the source/drain region contains impurities at a concentration of 5×

10¹⁹ cm<sup>−

3</sup> or lower.

10. A solid-state imaging device comprising:

a semiconductor region of a first conductivity type;

a plurality of unit pixels; and

a peripheral circuit located in a peripheral region of the plurality of unit pixels, and including a plurality of peripheral transistors; and

an insulating film isolating the plurality of peripheral transistors from each other

an impurity diffusion layer in the semiconductor region, wherein

each of the unit pixels includes

a photoelectric converter above the semiconductor region,

an amplifier transistor in the semiconductor region, including a gate electrode connected to the photoelectric converter, and

a reset transistor in the semiconductor region, configured to reset a potential of the gate electrode of the amplifier transistor,

the amplifier transistor and the reset transistor being electrically isolated from each other by the impurity diffusion layer.

14. The solid-state imaging device of claim 10, wherein the insulating film is disposed in the semiconductor region.

15. The solid-state imaging device of claim 10, wherein the insulating film is a shallow trench isolation (STI) region.