Bottom spacer formation for vertical transistor

• US 9,773,901 B1
• Filed: 10/26/2016
• Issued: 09/26/2017
• Est. Priority Date: 10/26/2016
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Gluschenkov, Oleg, Mehta, Sanjay C., Mochizuki, Shogo, Reznicek, Alexander
• Primary Examiner(s): Ghyka, Alexander
• Application Number:
  US15/335,105
• Time in Patent Office: 335 Days
• Field of Search: None
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers
• CPC Class Codes: H01L 29/66666 Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence

Abstract

A bilayer of silicon dioxide and silicon nitride is formed on exposed surfaces of at least one semiconductor fin having a bottom source/drain region located at the footprint, and on each side, of the at least one semiconductor fin. An upper surface of each horizontal portion of the silicon nitride layer is then carbonized, and thereafter non-carbonized vertical portions of the silicon nitride layer are removed. Next, the carbonized portions of the silicon nitride layer are removed, and thereafter the vertical portions of the silicon dioxide layer are removed from sidewalls of the at least one semiconductor fin utilizing each remaining portion of the silicon nitride layer as an etch mask A bottom spacer structure is provided on each bottom source/drain region in which each bottom spacer structure includes a remaining portion of the silicon dioxide layer and the remaining portion of the silicon nitride layer.

Claims

1. A method of forming a semiconductor structure, the method comprising:

forming at least one semiconductor fin extending upward from a surface of a substrate, wherein a bottom source/drain region is located at the footprint, and on each side, of the at least one semiconductor fin;

forming a dielectric material stack of, from bottom to top, a silicon dioxide layer and a silicon nitride layer on exposed surfaces of each bottom source/drain region and the at least one semiconductor fin;

carbonizing an upper surface of each horizontal portion of the silicon nitride layer;

removing non-carbonized vertical portions of the silicon nitride layer;

removing the carbonized portions of the silicon nitride layer; and

removing vertical portions of the silicon dioxide layer from sidewalls of the at least one utilizing each remaining portion of the silicon nitride layer as an etch mask to provide a bottom spacer structure located on each bottom source/drain region, each bottom spacer structure comprises a remaining portion of the silicon dioxide layer and the remaining portion of the silicon nitride layer.

2. The method of claim 1, wherein the remaining portion of the silicon nitride layer is entirely separated from the at least one semiconductor fin by a first portion of the remaining portion of the silicon dioxide layer and entirely separated from the bottom source/drain region by a second portion of the remaining portion of the silicon dioxide layer.

3. The method of claim 1, wherein said carbonizing comprises a directional plasma carbon deposition process.

4. The method of claim 3, wherein the directional plasma carbon deposition process is performed utilizing an energy of 100 eV or less.

5. The method of claim 1, wherein the directional plasma carbon deposition process comprises generating a plasma from a carbon-containing ambient and performing the carbonizing at a temperature from 50°

C. to 450°

C.

6. The method of claim 1, wherein the removing the vertical portions of the silicon dioxide layer comprises a dry isotropic etching process.

7. The method of claim 1, further comprising:

forming a functional gate structure located on each side of the at least one semiconductor fin and above the bottom spacer structure;

forming a top spacer located on each functional gate structure and contacting a sidewall of a portion of the at least one semiconductor fin; and

forming a top source/drain structure extending from each sidewall of an upper portion of the at least one semiconductor fin.

8. The method of claim 7, wherein the forming the top source/drain structure comprises an epitaxial growth process.

9. The method of claim 7, wherein each top source/drain structure has a faceted surface.

10. The method of claim 7, wherein each top source/drain structure has a non-faceted surface.