Zero-current crossing detection circuits

• US 9,774,258 B2
• Filed: 08/10/2015
• Issued: 09/26/2017
• Est. Priority Date: 08/10/2015
• Status: Active Grant

• Current Assignee: NXP USA, Inc. (NXP Semiconductors NV)
• Original Assignee: NXP USA, Inc. (NXP Semiconductors NV)
• Inventors: Campos, Marcelo de Paula
• Primary Examiner(s): Torres-Rivera, Alex
• Application Number:
  US14/822,294
• Publication Number:
  US 20170047840A1
• Time in Patent Office: 778 Days
• Field of Search: 323242, 323243, 323282, 323288, 323326
• CPC Class Codes: G01R 19/00 Arrangements for measuring currents or voltages or for indicating presence or sign thereof G01R5/00 takes precedence; for measuring bioelectric currents or voltages A61B5/24
• CPC Class Codes: G01R 19/175 Indicating the instants of passage of current or voltage through a given value, e.g. passage through zero
• CPC Class Codes: H02M 1/0009 Devices or circuits for detecting current in a converter
• CPC Class Codes: H02M 3/158 including plural semiconductor devices as final control devices for a single load
• CPC Class Codes: H02M 3/1588 comprising at least one synchronous rectifier element H02M3/1582, H02M3/1584 take precedence
• CPC Class Codes: Y02B 70/10 Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Abstract

Systems and methods for zero-current crossing detection circuits. In some embodiments, a circuit may include a buck converter comprising a high-side switch, a low-side switch, and an inductor; a zero-current crossing detection circuit comprising a reference switch coupled to a current source, where the reference switch is controllable conjointly with the low-side switch; an amplifier coupled to: (a) a first node between the current source and reference switch, where in operation the first node has a positive voltage value during an interval of interest, and a (b) second node between the low-side switch and the inductor, where in operation the second node has a negative voltage value during the interval of interest; and a comparator coupled to the amplifier, the comparator configured to output a flag in response to a detection that a decreasing current through the inductor has reached a predetermined value.

Claims

1. A circuit, comprising:

a buck converter comprising a high-side switch, a low-side switch, and an inductor;

a zero-current crossing detection circuit comprising a reference switch coupled to a current source, wherein the reference switch is controllable conjointly with the low-side switch;

an amplifier coupled to;

(a) a first node between the current source and the reference switch, wherein the first node has a positive voltage value during an interval of interest, and (b) a second node between the low-side switch and the inductor, wherein the second node has a negative voltage value during the interval of interest; and

a comparator coupled to the amplifier, the comparator configured to output a flag signal in response to a detection that a decreasing current through the inductor has reached a predetermined value.

2. The circuit of claim 1, wherein the current source is configured to set the predetermined value to a selected amount greater than zero, the selected amount configured to compensate for a delay between the detection and a subsequent turning off of the low-side switch to block the decreasing current through the inductor.

3. The circuit of claim 1, wherein the buck converter further comprises a capacitor coupled to the inductor and to ground.

4. The circuit of claim 3, further comprising an electrical load coupled in parallel with the capacitor.

5. The circuit of claim 4, wherein the high-side switch is a P-type metal-oxide-semiconductor (PMOS) transistor, the low-side switch is an N-type metal-oxide-semiconductor (NMOS) transistor, and the reference switch is another NMOS transistor.

6. The circuit of claim 5, wherein gate terminals of the low-side switch and the reference switch are coupled to each other.

7. The circuit of claim 6, wherein the reference switch occupies a silicon area that is between 1,000 to 10,000 times smaller than a silicon area occupied by the low-side switch, and wherein the reference switch and the low-side switch are disposed in close proximity to one another to reduce a temperature difference between them.

8. The circuit of claim 1, wherein the amplifier has differential inputs coupled to the first and second nodes and differential outputs coupled to the comparator.

9. The circuit of claim 1, further comprising a set of control switches configured to enable, in an alternating manner, a calibration mode of operation when the low-side switch is open, and a normal mode of operation when the low-side switch is closed.

10. A zero-current crossing detection circuit, comprising:

a current source;

a reference switch coupled to the current source at a first node, wherein a gate terminal of the reference switch is coupled to a gate terminal of a low-side switch of a DC-to-DC converter, the DC-to-DC converter comprising;

(a) a high-side switch coupled to the low-side switch at a second node; and

(b) an inductor coupled to the second node, wherein in operation the first node has a positive voltage and the second node has a negative or a positive voltage depending upon the operation cycle;

a comparator configured to output a flag signal in response to a detection that a decreasing current through the inductor has reached a predetermined value greater than zero, wherein the predetermined value is selected to compensate for a delay between the detection and a subsequent turning off of the low-side switch to block the decreasing current before it reaches or drops below zero; and

an amplifier having a pair of differential inputs coupled to the first and second nodes and a pair of differential outputs coupled to the comparator.

11. The zero-current crossing detection circuit of claim 10, wherein the DC-to-DC converter is a buck converter.

12. The zero-current crossing detection circuit of claim 10, wherein the high-side switch is a P-type metal-oxide-semiconductor (PMOS) transistor, the low-side switch is an N-type metal-oxide-semiconductor (NMOS) transistor, and the reference switch is another NMOS transistor.

13. The zero-current crossing detection circuit of claim 10, wherein the reference switch occupies a silicon area that is between 1,000 to 10,000 times smaller than a silicon area occupied by the low-side switch.

14. The zero-current crossing detection circuit of claim 10, further comprising a set of control switches configured to enable a calibration mode of operation when the low-side switch is open, and a normal mode of operation when the low-side switch is closed.

15. An electronic device, comprising:

a DC-to-DC converter; and

a zero-current crossing detection circuit coupled to the DC-to-DC converter, the zero-crossing detection circuit configured to output a flag signal in response to a decreasing current through an inductor within the DC-to-DC converter having reached a predetermined value, at least in part, by comparing;

(a) a positive voltage at a first node between a current source and a reference switch against (b) a negative voltage at a second node coupled to the inductor.

16. The electronic device of claim 15, wherein the DC-to-DC converter includes a high-side switch coupled to a low-side switch at the second node, and wherein the predetermined value is greater than zero and selected to compensate for a delay between a time when the decreasing current reaches the predetermined value and a subsequent turning off of the low-side switch to block the decreasing current before it reaches or drops below zero.

17. The electronic circuit of claim 16, further comprising:

an amplifier having a pair of differential inputs and a pair of differential outputs, the pair of differential inputs coupled to the first and second nodes; and

a comparator coupled to the pair of differential outputs, the comparator configured to output the flag signal in response to the decreasing current through the inductor having reached zero.

18. The electronic device of claim 16, further comprising a set of control switches configured to enable a calibration mode of operation when the low-side switch is open, and a normal mode of operation when the low-side switch is closed.