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All-digital-phase-locked-loop having a time-to-digital converter circuit with a dynamically adjustable offset delay

  • US 9,774,336 B2
  • Filed: 12/20/2015
  • Issued: 09/26/2017
  • Est. Priority Date: 12/19/2014
  • Status: Active Grant
First Claim
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1. An all-digital-phase-locked-loop (ADPLL) comprising:

  • a digitally controlled oscillator (DCO) arranged to generate a DCO output signal from a frequency code word (FCW); and

    a feedback loop comprising a set of components for controlling the DCO, wherein the set of components comprises;

    a time-to-digital converter (TDC) configured for phase detection within a predetermined observation window, wherein the TDC is arranged to define the predetermined observation window by receiving at least a reference signal having a first offset delay and an enable signal having a second offset delay, and to generate a TDC output code indicative of a phase difference between the reference signal and the enable signal measured within the predetermined observation window;

    a subset of components arranged to generate the enable signal from the DCO output signal, wherein the generated enable signal contains a transition edge derived from the DCO output signal, and wherein the enable signal is arranged to activate the TDC to measure the phase difference between the reference signal and the enable signal within the predetermined observation window; and

    an offset calibration system connected to the TDC output, wherein the offset calibration system, when activated, is arranged to evaluate a difference between the first and second offset delay values by monitoring the TDC output code generated over a predetermined period of time, and to adjust the difference between the first and second offset delay values to position the predetermined observation window with respect to the reference signal, and thereby to adjust the activation of the TDC so that the TDC operates within the predetermined observation window.

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