All-digital-phase-locked-loop having a time-to-digital converter circuit with a dynamically adjustable offset delay

• US 9,774,336 B2
• Filed: 12/20/2015
• Issued: 09/26/2017
• Est. Priority Date: 12/19/2014
• Status: Active Grant

• Current Assignee: Stichting Imec Nederland
• Original Assignee: Stichting Imec Nederland
• Inventors: Liu, Yao-Hong
• Primary Examiner(s): Skibinski, Thomas
• Application Number:
  US14/975,834
• Publication Number:
  US 20160182067A1
• Time in Patent Office: 646 Days
• Field of Search: 327147-163, 375373-376, 331 1 R, 331 1 A, 331 18, 331 34, 331 44, 331 65, 331 66, 331175, 331176
• CPC Class Codes: G04F 10/005 Time-to-digital converters [TDC] analog-to-digital converters with intermediate conversion to time or phase H03M1/50, H03M1/60
• CPC Class Codes: H03L 2207/50 All digital phase-locked loop
• CPC Class Codes: H03L 7/0814 the phase shifting device being digitally controlled
• CPC Class Codes: H03L 7/091 the phase or frequency detector using a sampling device H03L7/087 takes precedence
• CPC Class Codes: H03L 7/0991 the oscillator being a digital oscillator, e.g. composed of a fixed oscillator followed by a variable frequency divider H03L7/0995 takes precedence; fixed oscillators with means for selecting among various phases H03L7/0814

Abstract

An all-digital-phase-locked-loop (ADPLL) includes a digitally controlled oscillator (DCO) arranged to generate a DCO output signal, and a feedback loop comprising a set of components for controlling the DCO. The set of components comprise: a time-to-digital converter (TDC) arranged to generate a TDC output code indicative of the phase difference between the reference signal and the enable signal measured within the predetermined observation window; a subset of components arranged to generate the enable signal from the DCO output signal; and an offset calibration system connected to the TDC output, which when activated is arranged to evaluate the difference between the first and second offset delay values by monitoring the TDC output code generated over a predetermined period of time, and to adjust the difference to position the predetermined observation window with respect to the reference signal.

Claims

1. An all-digital-phase-locked-loop (ADPLL) comprising:

a digitally controlled oscillator (DCO) arranged to generate a DCO output signal from a frequency code word (FCW); and

a feedback loop comprising a set of components for controlling the DCO, wherein the set of components comprises;

a time-to-digital converter (TDC) configured for phase detection within a predetermined observation window, wherein the TDC is arranged to define the predetermined observation window by receiving at least a reference signal having a first offset delay and an enable signal having a second offset delay, and to generate a TDC output code indicative of a phase difference between the reference signal and the enable signal measured within the predetermined observation window;

a subset of components arranged to generate the enable signal from the DCO output signal, wherein the generated enable signal contains a transition edge derived from the DCO output signal, and wherein the enable signal is arranged to activate the TDC to measure the phase difference between the reference signal and the enable signal within the predetermined observation window; and

an offset calibration system connected to the TDC output, wherein the offset calibration system, when activated, is arranged to evaluate a difference between the first and second offset delay values by monitoring the TDC output code generated over a predetermined period of time, and to adjust the difference between the first and second offset delay values to position the predetermined observation window with respect to the reference signal, and thereby to adjust the activation of the TDC so that the TDC operates within the predetermined observation window.

2. The ADPLL of claim 1, wherein the offset calibration system further comprises:

an offset calibration unit connected to the TDC output and arranged to evaluate the difference between the first and second offset delay values, and to generate a delay adjustment control signal; and

a variable delay unit connected to the offset calibration unit and arranged to adjust the first offset delay on the basis of the delay adjustment control signal.

3. The ADPLL of claim 2, wherein the variable delay unit is part of the TDC.

4. The ADPLL of claim 1, wherein the offset calibration system is arranged to adjust the difference between the first and second offset delay values in such a way that a transition edge of the reference signal is positioned substantially in a middle of the predetermined observation window.

5. The ADPLL of claim 1, wherein the offset calibration system is arranged to adjust the difference between the first and second offset delay values in such a way that a transition edge of the reference signal is positioned substantially in a middle of a TDC transfer curve.

6. The ADPLL of claim 1, wherein the offset calibration system is further arranged to evaluate the difference between the first and second offset delay values by counting the number of ones and zeros generated by a most significant bit (MSB) of the TDC output code.

7. The ADPLL of claim 6, wherein the offset calibration system comprises a TDC offset control unit arranged to increase the first offset delay when the number of zeros is greater than the number of ones, as generated by the MSB of the TDC output code.

8. The ADPLL of claim 6, wherein the offset calibration system comprises a TDC offset control unit arranged to decrease the first offset delay when the number of ones is greater than the number of zeros, as generated by the MSB of the TDC output code.

9. The ADPLL of claim 1, wherein the feedback loop further comprises components arranged to detect a coarse part of a phase, and a fine part of the phase.

10. The ADPLL of claim 1, wherein the feedback loop further comprises components arranged to detect an integer part of the phase, and a fractional part of the phase.

11. The ADPLL of claim 1, wherein the TDC is a flash TDC.

12. The ADPLL of claim 1, wherein the offset calibration system is connected directly to the TDC output.

13. A method for operating an all-digital-phase-locked-loop (ADPLL) comprising a digitally controlled oscillator (DCO) arranged to generate a DCO output signal, and a feedback loop comprising a set of components for controlling the DCO, the method comprising:

activating a time-to-digital converter (TDC) configured for phase detection within a predetermined observation window, wherein the TDC is arranged to define the predetermined observation window by receiving at least a reference signal having a first offset delay and an enable signal having a second offset delay, wherein activating the TDC further comprises;

providing the reference signal to the TDC, and

generating the enable signal from the DCO output signal, wherein the generated enable signal contains a transition edge derived from the DCO output signal, and wherein the enable signal is arranged to activate the TDC to measure a phase difference between the reference signal and the enable signal within the predetermined observation window;

generating a TDC output code indicative of the phase difference between the reference signal and the enable signal measured within the predetermined observation window; and

performing, using a calibration system connected to the TDC output, an offset delay calibration, wherein performing the offset delay calibration comprises;

evaluating a difference between the first and second offset delay values by monitoring the TDC output code generated over a predetermined period of time, and

adjusting the difference between the first and second offset delay values to position the predetermined observation window with respect to the reference signal, and thereby activating the TDC within the predetermined observation window.

14. The method of claim 13, wherein performing the offset delay calibration further comprises:

generating a delay adjustment control signal based on the difference between the first and second offset delay values; and

applying the delay adjustment control signal to a variable delay unit to adjust the first offset delay.

15. The method of claim 13, wherein the offset delay calibration is performed off-line.

16. The method of claim 13, wherein the offset calibration is performed on-line during a frequency acquisition stage before activating the TDC for phase locking.

17. The method of claim 13, wherein the calibration system is connected directly to the TDC output.