Solid state image sensor with enhanced charge capacity and dynamic range

• US 9,774,801 B2
• Filed: 12/05/2014
• Issued: 09/26/2017
• Est. Priority Date: 12/05/2014
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: Hseih, Biay-Cheng, Goma, Sergiu Radu
• Primary Examiner(s): Haskins, Twyler
• Assistant Examiner(s): TEJANO, DWIGHT ALEX C
• Application Number:
  US14/561,845
• Publication Number:
  US 20160165159A1
• Time in Patent Office: 1,026 Days
• Field of Search: 257447
• CPC Class Codes: H01L 27/14632 Wafer-level processed structures
• CPC Class Codes: H01L 27/14634 Assemblies, i.e. Hybrid structures
• CPC Class Codes: H01L 27/14641 Electronic components shared by two or more pixel-elements, e.g. one amplifier shared by two pixel elements
• CPC Class Codes: H01L 27/14687 Wafer level processing
• CPC Class Codes: H04N 2209/046 Colour interpolation to calculate the missing colour values
• CPC Class Codes: H04N 23/741 by increasing the dynamic range of the image compared to the dynamic range of the electronic image sensors
• CPC Class Codes: H04N 23/815 for controlling the resolution by using a single image
• CPC Class Codes: H04N 25/134 based on three different wavelength filter elements
• CPC Class Codes: H04N 25/585 with pixels having different sensitivities within the sensor, e.g. fast or slow pixels or pixels having different sizes
• CPC Class Codes: H04N 25/70 SSIS architectures; Circuits associated therewith
• CPC Class Codes: H04N 25/778 comprising amplifiers shared between a plurality of pixels, i.e. at least one part of the amplifier must be on the sensor array itself
• CPC Class Codes: H04N 25/79 Arrangements of circuitry being divided between different or multiple substrates, chips or circuit boards, e.g. stacked image sensors

Abstract

Certain aspects relate to imaging systems and methods for manufacturing imaging systems and image sensors. The imaging system includes a pixel array including a plurality of pixels, the pixels configured to generate a charge when exposed to light and disposed on a first layer. The imaging system further includes a plurality of pixel circuits for reading light integrated in the pixels coupled thereto, each of the plurality of pixel circuits comprising one or more transistors shared between a subset of the plurality of the pixels, the one or more transistors disposed on a second layer different than the first layer. The imaging system further includes a plurality of floating diffusion nodes configured to couple each of the plurality of pixels to the plurality of pixel circuits.

Claims

1. An imaging system comprising:

a plurality of pixels configured to convert light into a charge, each pixel comprising;

a photodiode,

a transfer gate,

a storage capacitor electrically connected in series with the photodiode via the transfer gate disposed between the photodiode and the storage capacitor, the storage capacitor having a capacitance for storage of an accumulated charge representing a plurality of charge dumps from the connected photodiode, each of the plurality of charge dumps comprising a charge representative of the light integrated in the connected photodiode, and

a timing circuit electrically connected in series with the storage capacitor, the timing circuit configured to control the flow of charge from the storage capacitor to a floating diffusion node;

one or more amplifier transistors configured to convert a charge from the plurality of pixels;

one or more selection transistors configured to select a row or column of the plurality of pixels to be read out;

one or more reset transistors configured to reset at least one of the plurality of pixels;

a pixel array including the plurality of pixels arranged in one or more shared pixel architectures, the pixel array configured to independently control the transfer gate of each pixel to dump each of the plurality of charge dumps from the respective photodiode to the respective storage capacitor and independently control the timing circuit of each pixel so that charge dumps from each storage diode to the floating diffusion node occur one pixel at a time;

a first silicon layer upon which the plurality of pixels are disposed; and

a second silicon layer upon which at least one of the one or more amplifier transistors, selection transistors, and reset transistors are disposed.

2. The imaging system of claim 1, wherein the floating diffusion node is disposed on the first silicon layer and electrically coupled to the one or more amplifier transistors disposed on the second silicon layer.

3. The imaging system of claim 2, wherein the floating diffusion node disposed on the first silicon layer is electrically coupled to the one or more amplifier transistors disposed on the second silicon layer via a fine-pitch hybrid bond.

4. The imaging system of claim 2, wherein the floating diffusion node disposed on the first silicon layer is electrically coupled to the one or more amplifier transistors disposed on the second silicon layer via a fusion bond.

5. The imaging system of claim 1, wherein the one or more shared pixel architectures forming the pixel array are arranged in an interlaced manner and comprise the one or more amplifier transistors, one or more selection transistors, and one or more reset transistors being shared by at least a subset of pixels of the plurality of pixels.

6. The imaging system of claim 1, wherein one of the amplifier transistors, one of the selection transistors, and one of the reset transistors are shared among at least two pixels of the plurality of pixels.

7. The imaging system of claim 1, wherein, in each pixel, the timing circuit is connected in series with the corresponding transfer gate and the corresponding photodiode.

8. The imaging system of claim 1, wherein each of the shared pixel architectures comprises

the one or more amplifier transistors configured to receive the accumulated charge from the storage capacitor of each pixel and

the one or more selection transistors configured to activate the one or more amplifier transistors of a selected row of the plurality of pixels.

9. The imaging system of claim 1, wherein the photodiode of each pixel is configured to integrate light and convey the integrated light via the transfer gate of each pixel connected to the photodiode.

27. The imaging system of claim 1, wherein the pixel array being configured to independently control the transfer gate of each pixel to dump each of the plurality of charge dumps from the photodiode to the storage capacitor comprises the pixel array being configured to control each transfer gate of the plurality of pixels to transfer the charge accumulated in the respective photodiode to the respective storage capacitor independent of each other transfer gate of the plurality of pixels.

10. An imaging system comprising:

a plurality of sensor circuits configured to generate a charge when exposed to light from a target scene, each sensor circuit including;

a photodiode,

a transfer gate connected to the photodiode,

a storage capacitor coupled in series with the photodiode, the transfer gate disposed between the photodiode and the storage capacitor, the storage capacitor having a capacitance for storage of an accumulated charge representing a plurality of charge dumps from the coupled photodiode, each of the plurality of charge dumps comprising a charge representative of the light integrated in the coupled photodiode, and

a timing circuit electrically coupled in series with the storage capacitor and to a floating diffusion node, the transfer gate disposed therebetween and configured to control the flow of charge from the storage capacitor to the floating diffusion node;

a plurality of readout circuits, each readout circuit comprising at least one of a reset transistor, a row selection transistor, and an amplifying transistor;

a plurality of shared sensor architectures comprising two or more of the plurality of sensor circuits;

a sensor array including the plurality of sensor circuits, the sensor array configured to independently control the transfer gate of each sensor circuit to dump each of the plurality of charge dumps from the respective photodiode to the respective storage capacitor and independently control the timing circuit of each sensor circuit so that charge dumps from each storage diode to the floating diffusion node occur one sensor circuit at a time;

a first layer of silicon including the plurality of shared sensor architectures; and

a second layer of silicon including the plurality of readout circuits, the second layer positioned relative to the first layer in the imaging system such that the first layer is exposed to light incident on the imaging system from a target scene.

11. The imaging system of claim 10, wherein the amplifying transistor is configured to convert a charge from one or more sensor circuits.

12. The imaging system of claim 10, wherein the plurality of sensor circuits in the sensor array are arranged in a Bayer color pixel arrangement.

13. The imaging system of claim 10, further comprising at least one of a row and a column bus readout path disposed on the first silicon layer, wherein the at least one of the row and column readout path is coupled with a readout circuit disposed on the second layer of silicon.

14. The imaging system of claim 10, wherein the floating diffusion node is electrically coupled to one of the plurality of shared sensor architectures of the first silicon layer and one of the plurality of readout circuits of the second silicon layer via a fine- pitch hybrid bond.

15. The imaging system of claim 10, further comprising at least one of a row and a column bus readout path disposed on the first silicon layer electrically coupled to a readout circuit disposed on the second silicon layer, via a fusion bond.

16. An imaging system comprising:

a pixel array including a plurality of pixels configured to generate a charge when exposed to light, each of the plurality of pixels including a photodiode, a transfer gate connected to the photodiode, a storage capacitor electrically coupled in series with the photodiode, the transfer gate disposed between the photodiode and the storage capacitor, the storage capacitor having a capacitance for storage of an accumulated charge representing a plurality of the charge dumps from the coupled photodiode, each of the plurality of charge dumps comprising a charge representative of the light integrated in the coupled photodiode, and a timing circuit electrically coupled in series with the storage capacitor and configured to control the flow of charge from the coupled storage capacitor to a floating diffusion node;

a plurality of pixel readout circuits for reading light integrated in pixels coupled thereto, each of the plurality of pixel readout circuits comprising one or more transistors shared between at least a subset of the plurality of the pixels, the one or more transistors disposed on a second layer different than the first layer; and

a plurality of floating diffusion nodes configured to couple each of the plurality of pixels to the plurality of pixel readout circuits, wherein the pixel array is configured to independently control the transfer gate of each pixel to dump each of the plurality of charge dumps from the photodiode to the storage capacitor and independently control the timing circuit of each pixel so that charge dumps from each storage diode to the floating diffusion node occur one pixel at a time.

17. The imaging system of claim 16, wherein the floating diffusion node is connected between the pixel readout circuit of each of at least two pixels and the storage capacitor of each pixel coupled thereto.

18. The imaging system of claim 17, wherein each pixel readout circuit comprises a reset transistor configured to reset at least one of the floating diffusion node and the photodiode and the storage capacitor of at least one pixel to a predetermined charge level.

19. The imaging system of claim 17, wherein the floating diffusion node is electrically coupled to the one or more transistors disposed on the second silicon layer via a fine-pitch hybrid bond.

20. The imaging system of claim 17, wherein the floating diffusion node is electrically coupled to the one or more transistors disposed on the second silicon layer via a fusion bond.

21. The imaging system of claim 16, wherein the one or more transistors includes an amplifier, and wherein the imaging system further comprises an analog to digital converter in communication with the amplifier to receive an amplified signal and convert the amplified signal into a digital signal, wherein the analog to digital converter is disposed on a third layer different from the first and second layers.

22. A method of manufacturing a 3D stacked image sensor, comprising:

forming a pixel array on a first silicon layer, the pixel array including a plurality of pixels arranged in one or more shared pixel architectures, each of the plurality of pixels comprising;

a photodiode, a transfer gate coupled to the photodiode, a storage capacitor electrically coupled in series with the photodiode, wherein the transfer gate is disposed between the photodiode and the storage capacitor, the storage capacitor having a capacitance for storage of an accumulated charge representing a plurality of charge dumps from the coupled photodiode, each of the plurality of charge dumps comprising a charge representative of the light integrated in the coupled photodiode , and a timing circuit electrically coupled in series with the storage capacitor, the timing circuit configured to control the flow of charge from the coupled storage capacitor to a floating diffusion node, wherein the pixel array is configured to independently control the transfer gate of each pixel to dump each of the plurality of charge dumps from the photodiode to the storage capacitor and independently control the timing circuit of each pixel so that charge dumps from each storage diode to the floating diffusion node occur one pixel at a time;

forming a readout circuit including at least one amplifier transistor, selection transistor, and reset transistor on a second silicon layer different from the first silicon layer; and

forming the floating diffusion node electrically coupling two or more pixels of the first silicon layer to one readout circuit of the second silicon layer.

23. The method of manufacturing of claim 22, further comprising disposing one or more processing components, configured to manipulate a signal received from the at least one transistor disposed on the second silicon layer, on a third silicon layer different from the first and second silicon layers.

24. The method of manufacturing of claim 22, wherein electrically coupling two or more pixels of the first silicon layer to one readout circuit of the second silicon layer comprises coupling via a fine-pitch hybrid bond.

25. The method of manufacturing of claim 22, wherein electrically coupling two or more pixels of the first silicon layer to one readout circuit of the second silicon layer via a fusion bond.

26. The method of manufacturing of claim 22, wherein the shared pixel architectures forming the pixel array are arranged in an interlaced manner and comprise one or more amplifier transistors, one or more selection transistors, and one or more reset transistors being shared by a subset of pixels of the plurality of pixels.