Method and apparatus for improving read performance of a solid state drive
First Claim
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1. A method for improving performance of a solid state drive, the method comprising:
- initiating, by a controller of the solid state drive, a repacking of data stored in a non-volatile memory of the solid state drive, wherein refreshing of the data stored in the non-volatile memory of the solid state drive is performed during the repacking of the data stored in the non-volatile memory of the solid state drive; and
performing the repacking of the data stored in the non-volatile memory of the solid state drive by placing logical blocks physically contiguously in an increasing order in pre-erased locations of the non-volatile memory of the solid state drive, wherein the placing of the logical blocks contiguously in the increasing order comprises placing logical blocks with consecutive numerically indicated addresses sequentially, starting from a lower numbered address and ending at a higher numbered address.
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Abstract
A controller of a solid state drive initiates a repacking of data stored in a non-volatile memory of the solid state drive, wherein refreshing of the data stored in the non-volatile memory of the solid state drive is performed during the repacking of the data stored in the non-volatile memory of the solid state drive. Logical blocks are placed physically contiguously in an increasing order in pre-erased locations of the non-volatile memory of the solid state drive while the data stored in the non-volatile memory of the solid state drive is being repacked.
10 Citations
24 Claims
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1. A method for improving performance of a solid state drive, the method comprising:
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initiating, by a controller of the solid state drive, a repacking of data stored in a non-volatile memory of the solid state drive, wherein refreshing of the data stored in the non-volatile memory of the solid state drive is performed during the repacking of the data stored in the non-volatile memory of the solid state drive; and performing the repacking of the data stored in the non-volatile memory of the solid state drive by placing logical blocks physically contiguously in an increasing order in pre-erased locations of the non-volatile memory of the solid state drive, wherein the placing of the logical blocks contiguously in the increasing order comprises placing logical blocks with consecutive numerically indicated addresses sequentially, starting from a lower numbered address and ending at a higher numbered address. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. An apparatus, comprising:
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a plurality of non-volatile memory chips; and a controller coupled to the plurality of non-volatile memory chips, wherein the controller is operable to; initiate, a repacking of data stored in the plurality of non-volatile memory chips, wherein refreshing of the data stored in the plurality of non-volatile memory chips is performed during the repacking of the data stored in the plurality of non-volatile memory chips; and perform the repacking of the data stored in the plurality of non-volatile memory chips by placing logical blocks physically contiguously in an increasing order in pre-erased locations of the plurality of non-volatile memory chips, wherein the placing of the logical blocks contiguously in the increasing order comprises placing logical blocks with consecutive numerically indicated addresses sequentially, starting from a lower numbered address and ending at a higher numbered address. - View Dependent Claims (10, 11, 12, 13, 14, 15, 16)
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17. A system, comprising:
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a solid state drive comprising a plurality of non-volatile memory chips; a display; and a processor coupled to the solid state drive and the display, wherein, the solid state drive is operable to; initiate, a repacking of data stored in the plurality of non-volatile memory chips, wherein refreshing of the data stored in the plurality of non-volatile memory chips is performed during the repacking of the data stored in the plurality of non-volatile memory chips; and perform the repacking of the data stored in the plurality of non-volatile memory chips by placing logical blocks physically contiguously in an increasing order in pre-erased locations of the plurality of non-volatile memory chips, wherein the placing of the logical blocks contiguously in the increasing order comprises placing logical blocks with consecutive numerically indicated addresses sequentially, starting from a lower numbered address and ending at a higher numbered address. - View Dependent Claims (18, 19, 20, 21, 22, 23, 24)
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Specification