Software digital front end (SoftDFE) signal processing

• US 9,778,902 B2
• Filed: 10/26/2012
• Issued: 10/03/2017
• Est. Priority Date: 10/27/2011
• Status: Expired due to Fees

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Azadet, Kameran, Li, Chengzhou, Molina, Albert, Othmer, Joseph H., Pinault, Steven C., Yu, Meng-Lin, Williams, Joseph, Perez, Ramon Sanchez, Chen, Jian-Guo
• Primary Examiner(s): Ngo, Chuong D
• Application Number:
  US13/701,374
• Publication Number:
  US 20140086356A1
• Time in Patent Office: 1,803 Days
• CPC Class Codes: G06F 17/15 Correlation function computation including computation of convolution operations arithmetic circuits for sum of products per se, e.g. multiply-accumulators G06F7/5443; digital filters, e.g. FIR, IIR, adaptive filters H03H17/00
• CPC Class Codes: G06F 5/01 for shifting, e.g. justifying, scaling, normalising digital stores in which the information is moved stepwise, e.g. shift-registers G11C19/00; digital stores in which the information circulates G11C21/00
• CPC Class Codes: G06F 9/3001 Arithmetic instructions
• CPC Class Codes: G06F 9/30036 Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
• CPC Class Codes: G06F 9/3895 for complex operations, e.g. multidimensional or interleaved address generators, macros
• CPC Class Codes: H03F 1/0288 using a main and one or several auxiliary peaking amplifiers whereby the load is connected to the main amplifier using an impedance inverter, e.g. Doherty amplifiers
• CPC Class Codes: H03F 1/3241 using predistortion circuits H03F1/3211, H03F1/3217 take precedence
• CPC Class Codes: H03F 1/3258 based on polynomial terms
• CPC Class Codes: H03F 2200/336 A I/Q, i.e. phase quadrature, modulator or demodulator being used in an amplifying circuit
• CPC Class Codes: H03F 2201/3209 the amplifier comprising means for compensating memory effects
• CPC Class Codes: H03F 2201/3212 Using a control circuit to adjust amplitude and phase of a signal in a signal path
• CPC Class Codes: H03F 2201/3224 Predistortion being done for compensating memory effects
• CPC Class Codes: H03F 2201/3233 Adaptive predistortion using lookup table, e.g. memory, RAM, ROM, LUT, to generate the predistortion
• CPC Class Codes: H03F 3/189 High-frequency amplifiers, e.g. radio frequency amplifiers
• CPC Class Codes: H03F 3/24 of transmitter output stages
• CPC Class Codes: H03H 17/06 Non-recursive filters
• CPC Class Codes: H03M 3/30 Delta-sigma modulation
• CPC Class Codes: H04B 1/0003 Software-defined radio [SDR] systems, i.e. systems wherein components typically implemented in hardware, e.g. filters or modulators/demodulators, are implented using software, e.g. by involving an AD or DA conversion stage such that at least part of the signal processing is performed in the digital domain digital baseband systems H04L25/00; digital modulation/demodulation H04L27/00; CDMA H04B1/707; TDMA H04B7/2643; image transmission H04N5/00
• CPC Class Codes: H04B 1/0475 with means for limiting noise, interference or distortion H04B1/0483 takes precedence
• CPC Class Codes: H04B 1/62 for providing a predistortion of the signal in the transmitter and corresponding correction in the receiver, e.g. for improving the signal/noise ratio
• CPC Class Codes: H04B 2001/0408 : with power amplifiers
• CPC Class Codes: H04L 1/0054 : Maximum-likelihood or sequential decoding, e.g. Viterbi, Fano, ZJ algorithms
• CPC Class Codes: H04L 25/02 : Details ; arrangements for supplying electrical power along data transmission lines systems for transmitting signals via power distribution lines H04B3/54
• CPC Class Codes: H04L 25/03 : Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
• CPC Class Codes: H04L 25/03178 : Arrangements involving sequence estimation techniques
• CPC Class Codes: H04L 25/03216 : using the M-algorithm
• CPC Class Codes: H04L 25/4917 : using multilevel codes
• CPC Class Codes: H04L 27/2334 : using filters
• CPC Class Codes: H04L 27/2623 : Reduction thereof by clipping

Abstract

Software Digital Front End (SoftDFE) signal processing techniques are provided. One or more digital front end (DFE) functions are performed on a signal in software by executing one or more specialized instructions on a processor to perform the one or more digital front end (DFE) functions on the signal, wherein the processor has an instruction set comprised of one or more of linear and non-linear instructions. A block of samples comprised of a plurality of data samples is optionally formed and the digital front end (DFE) functions are performed on the block of samples. The specialized instructions can include a vector convolution function, a complex exponential function, an x^k function, a vector compare instruction, a vector max( ) instruction, a vector multiplication instruction, a vector addition instruction, a vector sqrt( ) instruction, a vector 1/x instruction, and a user-defined non-linear instruction.

Claims

1. A method for performing a vector convolution function on a signal in software, comprising:

receiving, by a processor, the signal, wherein the signal comprises a plurality of data samples, and

performing, by the processor, the vector convolution function on the signal and a plurality of coefficients by executing, in response to a single software instruction, a single instruction of a hardware instruction set of the processor, wherein the single instruction comprises a vector convolution instruction,

wherein performing the vector convolution function comprises producing, for each of a plurality of time shifts, a finite impulse response output value based on the plurality of data samples and the plurality of coefficients,

wherein producing, for each of the plurality of time shifts, the finite impulse response output value comprises to produce, for each of the plurality of time shifts, only a portion of the finite impulse response output value based on the plurality of data samples and only a portion of each coefficient of the plurality of coefficients in one clock cycle of the processor.

2. The method of claim 1, wherein said processor comprises one or more of a digital signal processor or a vector processor.

3. The method of claim 1, wherein a plurality of signals from a plurality of processors are each processed on a separate processor.

4. The method of claim 1, further comprising performing, by the processor, a complex exponential function on the signal by executing, in response to a single complex exponentiation software instruction, a single complex exponentiation instruction of the hardware instruction set.

5. The method of claim 1 further comprising performing, by the processor, an x^k function on the signal by executing, in response to a single x^k software instruction, a single x^k instruction of the hardware instruction set.

6. The method of claim 1, further comprising performing, by the processor, a digital up conversion function that multiplies said signal by a complex exponential by executing, in response to a single up conversion software instruction, a single up conversion instruction of the hardware instruction set.

7. The method of claim 1 further comprising performing, by the processor, one or more user-defined non-linear instructions.

8. The method of claim 7, wherein said one or more user-defined non-linear instructions comprise at least one user-specified parameter.

9. The method of claim 8, wherein performing, by the processor, the one or more user defined non-linear instructions comprises:

invoking at least one functional unit that applies said non-linear function to an input value, x; and

generating an output corresponding to said non-linear function for said input value, x.

10. The method of claim 8, further comprising the step of loading said at least one user-specified parameter from memory into at least one register.

11. The method of claim 8, wherein said user-specified parameter comprises a look-up table storing values of said non-linear function for a finite number of input values.

12. The method of claim 1, wherein only the portion of each coefficient of the plurality of coefficients comprises only the first two bits of each coefficient of the plurality of coefficients, wherein each coefficient of the plurality of coefficients comprises more than two bits.

13. A processor for performing a vector convolution function on a signal in software, comprising:

a memory; and

at least one hardware device, coupled to the memory, operative to;

receive, by the at least one hardware device, the signal, wherein the signal comprises a plurality of data samples, and

perform, by the at least one hardware device, the vector convolution function on the signal and a plurality of coefficients by executing, in response to a single software instruction, a single instruction of a hardware instruction set of the processor, wherein the single instruction comprises a vector convolution instruction, wherein to perform the vector convolution function comprises to produce, for each of a plurality of time shifts, a finite impulse response output value based on the plurality of data samples and the plurality of coefficients,

wherein to produce, for each of the plurality of time shifts, the finite impulse response output value comprises to produce, for each of the plurality of time shifts, only a portion of the finite impulse response output value based on the plurality of data samples and only a portion of each coefficient of the plurality of coefficients in one clock cycle of the at least one hardware device.

14. The processor of claim 13, wherein only the portion of each coefficient of the plurality of coefficients comprises only the first two bits of each coefficient of the plurality of coefficients, wherein each coefficient of the plurality of coefficients comprises more than two bits.

15. The processor of claim 13, wherein said processor comprises one or more of a digital signal processor or a vector processor.

16. The processor of claim 13, wherein a plurality of signals from a plurality of processors are each processed on a separate processor.

17. The processor of claim 13, wherein the hardware device is further to perform a complex exponential function on the signal by executing, in response to a single complex exponentiation software instruction, a single complex exponentiation instruction of the hardware instruction set of the processor.

18. The processor of claim 13, wherein the hardware device is further to perform an x^k function on the signal by executing, in response to a single x^k software instruction, a single x^k instruction of the hardware instruction set of the processor.

19. The processor of claim 13, wherein the hardware device is further to perform a digital up conversion function that multiplies said signal by a complex exponential signal by executing, in response to a single up conversion software instruction, a single up conversion instruction of the hardware instruction set of the processor.

20. The processor of claim 13, wherein the hardware device is further to perform one or more user-defined non-linear instructions.

21. The processor of claim 20, wherein the one or more user-defined non-linear instructions comprises at least one user-specified parameter.

22. The processor of claim 21, wherein to perform the one or more user defined non-linear instructions comprises to:

invoke at least one functional unit that implements applies the non-linear function to an input value x; and

generate an output corresponding to the non-linear function for the input value x.

23. The processor of claim 21, wherein the hardware device is further to load the at least one user-specified parameter into at least one register.

24. The processor of claim 21, wherein the at least one user-specified parameter comprises a look-up table storing values of said non-linear function for a finite number of input values.

25. One or more non-transitory computer readable media comprising a plurality of instructions stored thereon that, when executed by at least one hardware device, causes the at least one hardware device to:

receive a signal, wherein the signal comprises a plurality of data samples;

perform a vector convolution function on the signal and a plurality of coefficients by executing, in response to a single software instruction, a single instruction of a hardware instruction set of the at least one hardware device, wherein the single instruction comprises a vector convolution instruction, wherein to perform the vector convolution function comprises to produce, for each of a plurality of time shifts, a finite impulse response output value based on the plurality of data samples and the plurality of coefficients,

wherein to produce, for each of the plurality of time shifts, the finite impulse response output value comprises to produce, for each of the plurality of time shifts, only a portion of the finite impulse response output value based on the plurality of data samples and only a portion of each coefficient of the plurality of coefficients in one clock cycle of the at least one hardware device.

26. The one or more non-transitory computer-readable storage media of claim 25, wherein only the portion of each coefficient of the plurality of coefficients comprises only the first two bits of each coefficient of the plurality of coefficients, wherein each coefficient of the plurality of coefficients comprises more than two bits.

27. The one or more non-transitory computer-readable storage media of claim 25, wherein the plurality of instructions further causes the hardware device to perform a complex exponential function on the signal by executing, in response to a single complex exponentiation software instruction, a single complex exponentiation instruction of the hardware instruction set.

28. The one or more non-transitory computer-readable storage media of claim 25, wherein the plurality of instructions further causes the hardware device to perform an x^k function on the signal by executing, in response to a single x^k software instruction, a single x^k instruction of the hardware instruction set.

29. The one or more non-transitory computer-readable storage media of claim 25, wherein the plurality of instructions further causes the hardware device to perform a digital up conversion function that multiplies said signal by a complex exponential signal by executing, in response to a single up conversion software instruction, a single up conversion instruction of the hardware instruction set.

30. The one or more non-transitory computer-readable storage media of claim 25, wherein the plurality of instructions further causes the hardware device to perform one or more user-defined non-linear instructions.

31. The one or more non-transitory computer-readable storage media of claim 30, wherein the one or more user-defined non-linear instructions comprises at least one user-specified parameter.

32. The one or more non-transitory computer-readable storage media of claim 31, wherein to perform the one or more user defined non-linear instructions comprises to:

invoke at least one functional unit that implements applies the non-linear function to an input value x; and

generate an output corresponding to the non-linear function for the input value x.

33. The one or more non-transitory computer-readable storage media of claim 31, wherein the plurality of instructions further causes the hardware device to load the at least one user-specified parameter into at least one register.

34. The one or more non-transitory computer-readable storage media of claim 31, wherein the at least one user-specified parameter comprises a look-up table storing values of said non-linear function for a finite number of input values.