Integrated circuit containing first and second DOEs of standard cell compatible, NCEM-enabled fill cells, with the first DOE including snake open configured fill cells, and the second DOE including metal island open configured fill cells
First Claim
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1. A monolithic integrated circuit (IC) that includes at least a source/drain (AA) layer, a source/drain contact (AACNT) layer, a source/drain silicide (TS) layer, a gate (GATE) layer, a gate contact (GATECNT) layer, a via to interconnect stack (V0) layer, a first wiring (M1) layer, a second wiring (M2) layer, and an M1-to-M2 via (V1) layer, said IC comprising at least:
- (i) a first design of experiments (DOE) that includes at least first and second non-contact electrical measurement (NCEM)-enabled fill cells, each of the first and second NCEM-enabled fill cells configured in a standard cell form, with first and second supply rails that extend horizontally across the cell and uniformly spaced GATE stripes that extend vertically across the cell, each of the first and second NCEM-enabled fill cells further including test area patterning that comprises at least first and second features, arranged in a snake open configuration, wherein the first feature is electrically connected to an NCEM pad and the second feature is electrically connected to a permanent or virtual ground, thereby enabling detection of an unintended open or resistance in the test area patterning using a non-contact (NC) measurement at the NCEM pad, the first and second NCEM-enabled fill cells further having at least one patterning difference that results in a different probability of detecting opens or resistances in the test area of the first NCEM-enabled fill cell versus the test area of the second NCEM-enabled fill cell; and
,(ii) a second DOE that includes at least first and second NCEM-enabled fill cells, each of the first and second NCEM-enabled fill cells configured in a standard cell form, with first and second supply rails that extend horizontally across the cell and uniformly spaced GATE stripes that extend vertically across the cell, each of the first and second NCEM-enabled fill cells further including test area patterning that comprises at least first and second features, arranged in a metal island open configuration, wherein the first feature is electrically connected to an NCEM pad and the second feature is electrically connected to a permanent or virtual ground, thereby enabling detection of an unintended open or resistance in the test area patterning using a NC measurement at the NCEM pad, the first and second NCEM-enabled fill cells further having at least one patterning difference that results in a different probability of detecting opens or resistances in the test area of the first NCEM-enabled fill cell versus the test area of the second NCEM-enabled fill cell;
wherein all of the NCEM-enabled fill cells in the first and second DOEs are configured in a compatible standard cell form, with identical spacing between the first and second supply rails and identical spacing between adjacent GATE stripes.
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Abstract
An IC includes first and second designs of experiments (DOEs), each comprised of at least two fill cells. The fill cells contain structures configured to obtain in-line data via non-contact electrical measurements (“NCEM”). The first DOE contains fill cells configured to enable non-contact (NC) detection of snake opens, and the second DOE contains fill cells configured to enable NC detection of metal island opens.
216 Citations
11 Claims
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1. A monolithic integrated circuit (IC) that includes at least a source/drain (AA) layer, a source/drain contact (AACNT) layer, a source/drain silicide (TS) layer, a gate (GATE) layer, a gate contact (GATECNT) layer, a via to interconnect stack (V0) layer, a first wiring (M1) layer, a second wiring (M2) layer, and an M1-to-M2 via (V1) layer, said IC comprising at least:
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(i) a first design of experiments (DOE) that includes at least first and second non-contact electrical measurement (NCEM)-enabled fill cells, each of the first and second NCEM-enabled fill cells configured in a standard cell form, with first and second supply rails that extend horizontally across the cell and uniformly spaced GATE stripes that extend vertically across the cell, each of the first and second NCEM-enabled fill cells further including test area patterning that comprises at least first and second features, arranged in a snake open configuration, wherein the first feature is electrically connected to an NCEM pad and the second feature is electrically connected to a permanent or virtual ground, thereby enabling detection of an unintended open or resistance in the test area patterning using a non-contact (NC) measurement at the NCEM pad, the first and second NCEM-enabled fill cells further having at least one patterning difference that results in a different probability of detecting opens or resistances in the test area of the first NCEM-enabled fill cell versus the test area of the second NCEM-enabled fill cell; and
,(ii) a second DOE that includes at least first and second NCEM-enabled fill cells, each of the first and second NCEM-enabled fill cells configured in a standard cell form, with first and second supply rails that extend horizontally across the cell and uniformly spaced GATE stripes that extend vertically across the cell, each of the first and second NCEM-enabled fill cells further including test area patterning that comprises at least first and second features, arranged in a metal island open configuration, wherein the first feature is electrically connected to an NCEM pad and the second feature is electrically connected to a permanent or virtual ground, thereby enabling detection of an unintended open or resistance in the test area patterning using a NC measurement at the NCEM pad, the first and second NCEM-enabled fill cells further having at least one patterning difference that results in a different probability of detecting opens or resistances in the test area of the first NCEM-enabled fill cell versus the test area of the second NCEM-enabled fill cell; wherein all of the NCEM-enabled fill cells in the first and second DOEs are configured in a compatible standard cell form, with identical spacing between the first and second supply rails and identical spacing between adjacent GATE stripes. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
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Specification
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InventorsLam, Stephen, Ciplickas, Dennis, Brozek, Tomasz, Cheng, Jeremy, Comensoli, Simone, De, Indranil, Doong, Kelvin, Eisenmann, Hans, Fiscus, Timothy, Haigh, Jonathan, Hess, Christopher, Kibarian, John, Lee, Sherry, Liao, Marci, Lin, Sheng-Che, Matsuhashi, Hideki, Michaels, Kimon, O'Sullivan, Conor, Rauscher, Markus, Rovner, Vyacheslav, Strojwas, Andrzej, Strojwas, Marcin, Taylor, Carl, Vallishayee, Rakesh, Weiland, Larg, Yokoyama, Nobuharu
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Primary Examiner(s)Henry, Caleb
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Assistant Examiner(s)Belousov, Alexander
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Application NumberUS15/635,396Time in Patent Office97 DaysField of SearchUS Class CurrentCPC Class CodesG01R 31/303 of integrated circuits G01R...G06F 11/079 Root cause analysis, i.e. e...G06F 2111/04 Constraint-based CADG06F 30/30 Circuit designG06F 30/39 Circuit design at the physi...G06F 30/392 Floor-planning or layout, e...G06F 30/398 Design verification or opti...H01L 2027/11866 Gate electrode terminals or...H01L 2027/11875 Wiring region, routingH01L 2027/11888 More than 3 levels of metalH01L 21/823437 with a particular manufactu...H01L 21/823475 interconnection or wiring o...H01L 22/20 Sequence of activities cons...H01L 22/26 Acting in response to an on...H01L 22/32 Additional lead-in metallis...H01L 22/34 Circuits for electrically c...H01L 23/5226 Via connections in a multil...H01L 23/528 Geometry or layout of the i...H01L 27/0207 Geometrical layout of the c...H01L 27/088 the components being field-...View All
