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Apparatuses and methods involving accessing distributed sub-blocks of memory cells

  • US 9,779,791 B2
  • Filed: 11/14/2014
  • Issued: 10/03/2017
  • Est. Priority Date: 08/21/2012
  • Status: Active Grant
First Claim
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1. A memory device comprising:

  • multiple stacked arrays of memory cells having multiple blocks of memory extending across multiple of the stacked arrays, each memory block having multiple sub-blocks of memory cells, wherein all memory cells in a block are enabled to be accessed at the same time; and

    control circuitry coupled to the array of memory cells, the control circuitry configured to access memory cells of multiple sub-blocks of memory cells in a block extending across first and second arrays at the same time, wherein the multiple sub-blocks of a block extending in the first array are in different rows and different columns of the first array, and wherein the multiple sub-blocks of the block extending in the second array are in different rows and different columns of the second array.

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