Apparatuses and methods involving accessing distributed sub-blocks of memory cells
First Claim
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1. A memory device comprising:
- multiple stacked arrays of memory cells having multiple blocks of memory extending across multiple of the stacked arrays, each memory block having multiple sub-blocks of memory cells, wherein all memory cells in a block are enabled to be accessed at the same time; and
control circuitry coupled to the array of memory cells, the control circuitry configured to access memory cells of multiple sub-blocks of memory cells in a block extending across first and second arrays at the same time, wherein the multiple sub-blocks of a block extending in the first array are in different rows and different columns of the first array, and wherein the multiple sub-blocks of the block extending in the second array are in different rows and different columns of the second array.
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Abstract
Apparatuses and methods involving accessing distributed sub-blocks of memory cells are described. In one such method, distributed sub-blocks of memory cells in a memory array are enabled to be accessed at the same time. Additional embodiments are described.
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Citations
20 Claims
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1. A memory device comprising:
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multiple stacked arrays of memory cells having multiple blocks of memory extending across multiple of the stacked arrays, each memory block having multiple sub-blocks of memory cells, wherein all memory cells in a block are enabled to be accessed at the same time; and control circuitry coupled to the array of memory cells, the control circuitry configured to access memory cells of multiple sub-blocks of memory cells in a block extending across first and second arrays at the same time, wherein the multiple sub-blocks of a block extending in the first array are in different rows and different columns of the first array, and wherein the multiple sub-blocks of the block extending in the second array are in different rows and different columns of the second array. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A three-dimensional memory device comprising:
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multiple arrays of memory cells vertically arranged with one another, the multiple arrays having multiple blocks of memory cells extending across multiple vertically arranged arrays, each block having multiple sub-blocks arranged in rows and columns in the arrays; and control circuitry coupled to the array of memory cells, the control circuitry configured to access multiple sub-blocks of a block of memory cells extending across at least first and second of the vertically arranged arrays at the same time, wherein the block is distributed across the first and second arrays, with no accessed sub-block of multiple sub-blocks in the first array is in a corresponding row and column as another simultaneously accessed sub-block in the second array of the plurality of sub-blocks. - View Dependent Claims (9, 10, 11, 12, 13)
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14. A memory device comprising:
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multiple stacked arrays of memory cells having multiple memory blocks each extending across multiple of the stacked arrays, each memory block having multiple sub-blocks of memory cells in multiple of the stacked arrays; and control circuitry coupled to the array of memory cells, the control circuitry configured to receive a memory request and, in response to the memory request, access first data in a first sub-block of memory cells of a block of memory cells, the first sub-block located in a first of the stacked arrays, and access second data in a second sub-block of memory cells at the same time that the first data is being accessed, wherein the second sub-block is in a second of the stacked arrays, and wherein the first sub-block in the first array is not vertically adjacent the second sub-block in the second array. - View Dependent Claims (15, 16, 17)
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18. A memory system comprising:
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multiple vertically arranged arrays of memory cells having a plurality of memory blocks, each memory block extending across multiple of the vertically arranged arrays and having multiple sub-blocks of memory cells in each of the multiple arrays; and control circuitry coupled to the array of memory cells, the control circuitry configured to enable the sub-blocks of memory cells of a block extending across first and second of the vertically arrays to be accessed at the same time, each of the enabled sub-blocks in the first array, wherein each of the enabled sub-blocks in the first array are in different rows and columns in the array, and wherein each of the enabled sub-blocks in the second array are in different rows and columns in the array. - View Dependent Claims (19, 20)
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Specification