Apparatuses and methods involving accessing distributed sub-blocks of memory cells

• US 9,779,791 B2
• Filed: 11/14/2014
• Issued: 10/03/2017
• Est. Priority Date: 08/21/2012
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Tanzawa, Toru
• Primary Examiner(s): Ho, Hoai V
• Application Number:
  US14/542,244
• Publication Number:
  US 20150063022A1
• Time in Patent Office: 1,054 Days
• Field of Search: 365148, 365149, 3651851, 36523003, 36518511
• CPC Class Codes: G11C 11/4087 Address decoders, e.g. bit - or word line decoders; Multiple line decoders
• CPC Class Codes: G11C 13/0004 comprising amorphous/crystalline phase transition cells
• CPC Class Codes: G11C 13/003 Cell access
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/08 Address circuits; Decoders; Word-line control circuits
• CPC Class Codes: G11C 16/3427 Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written
• CPC Class Codes: G11C 5/025 Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device geometrical lay-out of the components in integrated circuits, H01L27/0207
• CPC Class Codes: G11C 5/063 Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
• CPC Class Codes: G11C 7/00 Arrangements for writing information into, or reading information out from, a digital store G11C5/00 takes precedence; auxiliary circuits for stores using semiconductor devices G11C11/4063, G11C11/413
• CPC Class Codes: G11C 7/02 with means for avoiding parasitic signals
• CPC Class Codes: G11C 8/10 Decoders
• CPC Class Codes: G11C 8/12 Group selection circuits, e.g. for memory block selection, chip selection, array selection
• CPC Class Codes: G11C 8/16 Multiple access memory array, e.g. addressing one storage element via at least two independent addressing line groups
• CPC Class Codes: G11C 8/18 Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals

Abstract

Apparatuses and methods involving accessing distributed sub-blocks of memory cells are described. In one such method, distributed sub-blocks of memory cells in a memory array are enabled to be accessed at the same time. Additional embodiments are described.

Claims

1. A memory device comprising:

multiple stacked arrays of memory cells having multiple blocks of memory extending across multiple of the stacked arrays, each memory block having multiple sub-blocks of memory cells, wherein all memory cells in a block are enabled to be accessed at the same time; and

control circuitry coupled to the array of memory cells, the control circuitry configured to access memory cells of multiple sub-blocks of memory cells in a block extending across first and second arrays at the same time, wherein the multiple sub-blocks of a block extending in the first array are in different rows and different columns of the first array, and wherein the multiple sub-blocks of the block extending in the second array are in different rows and different columns of the second array.

2. The memory device of claim 1, wherein the array of memory cells is an array of dynamic random access memory cells.

3. The memory device of claim 1, wherein the array of memory cells is an array of phase change memory cells.

4. The memory device of claim 1, wherein the array of memory cells are organized as a NAND array of memory cells.

5. The memory device of claim 1, further comprising a decoder circuit coupled to the array of memory cells and configured to enable a plurality of decoding signal lines to provide enable signals in response to decoding signals from the control circuitry.

6. The memory device of claim 1, further comprising driver circuits coupled to the control circuitry through a control logic circuit, wherein the driver circuits are configured to output signals from the array of memory cells in response to control signals from the control circuitry.

7. The memory device of claim 6, further comprising a sense/cache circuit coupled between the array of memory cells and the driver circuits.

8. A three-dimensional memory device comprising:

multiple arrays of memory cells vertically arranged with one another, the multiple arrays having multiple blocks of memory cells extending across multiple vertically arranged arrays, each block having multiple sub-blocks arranged in rows and columns in the arrays; and

control circuitry coupled to the array of memory cells, the control circuitry configured to access multiple sub-blocks of a block of memory cells extending across at least first and second of the vertically arranged arrays at the same time, wherein the block is distributed across the first and second arrays, with no accessed sub-block of multiple sub-blocks in the first array is in a corresponding row and column as another simultaneously accessed sub-block in the second array of the plurality of sub-blocks.

9. The memory device of claim 8, wherein the control circuitry is further configured to enable access lines coupled to the memory cells in the sub-blocks to receive programming voltages, read voltages, or erase voltages.

10. The memory device of claim 8, further comprising decoder circuits and the control circuitry is further configured to provide an enable signal for each enabled sub-block in response to a plurality of decoding signals from the decoder circuit.

11. The memory device of claim 8, wherein each of the memory cells in the array of memory cells is defined with reference to a first coordinate and a second coordinate in a coordinate system.

12. The memory device of claim 11, wherein each memory cell in the two-dimensional arrays is located with reference to an x-coordinate and a y-coordinate in a Cartesian coordinate system.

13. The memory device of claim 8, wherein the memory cells are located according to a Polar coordinate system.

14. A memory device comprising:

multiple stacked arrays of memory cells having multiple memory blocks each extending across multiple of the stacked arrays, each memory block having multiple sub-blocks of memory cells in multiple of the stacked arrays; and

control circuitry coupled to the array of memory cells, the control circuitry configured to receive a memory request and, in response to the memory request, access first data in a first sub-block of memory cells of a block of memory cells, the first sub-block located in a first of the stacked arrays, and access second data in a second sub-block of memory cells at the same time that the first data is being accessed, wherein the second sub-block is in a second of the stacked arrays, and wherein the first sub-block in the first array is not vertically adjacent the second sub-block in the second array.

15. The memory device of claim 14, wherein the control circuit configured to access the first data comprises the control circuit configured to write the first data to memory cells of the first sub-block and the control circuit configured to access the second data comprises the control circuit configured to write the second data to memory cells of the second sub-block.

16. The memory device of claim 14, wherein the control circuit configured to access the first data comprises the control circuit configured to erase the first data from memory cells of the first sub-block and the control circuit configured to access the second data comprises the control circuit configured to erase the second data from memory cells of the second sub-block.

17. The memory device of claim 14, wherein the control circuit configured to access the first data comprises the control circuit configured to read the first data from memory cells of the first sub-block and the control circuit configured to access the second data comprises the control circuit configured to read the second data from memory cells of the second sub-block.

18. A memory system comprising:

multiple vertically arranged arrays of memory cells having a plurality of memory blocks, each memory block extending across multiple of the vertically arranged arrays and having multiple sub-blocks of memory cells in each of the multiple arrays; and

control circuitry coupled to the array of memory cells, the control circuitry configured to enable the sub-blocks of memory cells of a block extending across first and second of the vertically arrays to be accessed at the same time, each of the enabled sub-blocks in the first array, wherein each of the enabled sub-blocks in the first array are in different rows and columns in the array, and wherein each of the enabled sub-blocks in the second array are in different rows and columns in the array.

19. The memory system of claim 18, wherein the control circuit is further configured to provide an enable signal for each enabled sub-block in response to a plurality of decoding signals in a decoder circuit.

20. The memory system of claim 18, wherein the enabled sub-blocks in the first array are in corresponding rows and columns to the enabled sub-blocks in the second array.