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Flash memory system

  • US 9,779,804 B2
  • Filed: 11/08/2016
  • Issued: 10/03/2017
  • Est. Priority Date: 09/30/2005
  • Status: Active Grant
First Claim
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1. A NAND flash memory device comprising:

  • at least two NAND flash memory banks being independently operable by having respective control circuitry, row decoding circuitry, sense amplifier circuitry and page buffer circuitry;

    a chip select input configured to receive a chip select signal;

    a clock input configured to receive a clock signal;

    a common command, address, data input configured to receive, all at different times, command data, address data and page data while the chip select signal is at an active low logic state, wherein the address data is including bank address data to identify the first NAND flash memory bank as addressed for performing a page program operation carried out thereon;

    a first control input configured to receive a first of two control signals;

    a second control input configured to receive a second of the two control signals;

    circuitry configured to execute the page program operation on the first NAND flash memory bank corresponding to the command data;

    a first bank status indicator configured to indicate that the first NAND flash memory bank is being utilized during the page program operation on the first NAND flash memory bank; and

    latch circuitry configured to;

    latch the command data while only the first of the two control signals is held at an active high logic state for at least a duration of time that the command data is received at the common input, andlatch the page data in synchronization with both rising and falling edges of the clock signal.

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