Flash memory system

• US 9,779,804 B2
• Filed: 11/08/2016
• Issued: 10/03/2017
• Est. Priority Date: 09/30/2005
• Status: Active Grant

• Current Assignee: MOSAID Technologies Inc. (f/k/a Conversant Intellectual Property Management)
• Original Assignee: Conversant Intellectual Property Management Inc (MOSAID Technologies Inc. (f/k/a Conversant Intellectual Property Management))
• Inventors: Oh, HakJune, Pyeon, Hong Beom, Kim, Jin-Ki
• Primary Examiner(s): AUDUONG, GENE NGHIA
• Application Number:
  US15/345,552
• Publication Number:
  US 20170076789A1
• Time in Patent Office: 329 Days
• Field of Search: 36518511, 36518512, 36518533, 36518517, 36518905, 36518915, 365221, 3652331, 365239
• CPC Class Codes: G06F 1/12 Synchronisation of different clock signals provided by a plurality of clock generators
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 11/5642 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/06 Auxiliary circuits, e.g. for writing into memory
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/16 for erasing blocks, e.g. arrays, words, groups
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/3445 Circuits or methods to verify correct erasure of nonvolatile memory cells
• CPC Class Codes: G11C 2207/107 Serial-parallel conversion of data or prefetch
• CPC Class Codes: G11C 7/1021 Page serial bit line access mode, i.e. using an enabled row address stroke pulse with its associated word line address and a sequence of enabled column address stroke pulses each with its associated bit line address
• CPC Class Codes: G11C 7/1051 Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
• CPC Class Codes: G11C 7/1078 Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits

Abstract

An apparatus, system, and method for controlling data transfer to an output port of a serial data link interface in a semiconductor memory is disclosed. In one example, a flash memory device may have multiple serial data links, multiple memory banks and control input ports that enable the memory device to transfer the serial data to a serial data output port of the memory device. In another example, a flash memory device may have a single serial data link, a single memory bank, a serial data input port, a control input port for receiving output enable signals. The flash memory devices may be cascaded in a daisy-chain configuration using echo signal lines to serially communicate between memory devices.

Claims

1. A NAND flash memory device comprising:

at least two NAND flash memory banks being independently operable by having respective control circuitry, row decoding circuitry, sense amplifier circuitry and page buffer circuitry;

a chip select input configured to receive a chip select signal;

a clock input configured to receive a clock signal;

a common command, address, data input configured to receive, all at different times, command data, address data and page data while the chip select signal is at an active low logic state, wherein the address data is including bank address data to identify the first NAND flash memory bank as addressed for performing a page program operation carried out thereon;

a first control input configured to receive a first of two control signals;

a second control input configured to receive a second of the two control signals;

circuitry configured to execute the page program operation on the first NAND flash memory bank corresponding to the command data;

a first bank status indicator configured to indicate that the first NAND flash memory bank is being utilized during the page program operation on the first NAND flash memory bank; and

latch circuitry configured to;

latch the command data while only the first of the two control signals is held at an active high logic state for at least a duration of time that the command data is received at the common input, and

latch the page data in synchronization with both rising and falling edges of the clock signal.

2. The NAND flash memory device as claimed in claim 1 wherein the common input is configured to receive, all at different times, second command data, second address data and second page data while the chip select signal is at the active low logic state and the first NAND flash memory bank is being utilized, wherein the second address data is including second bank address data to identify the second NAND flash memory bank as addressed for performing a second page program operation carried out thereon.

3. The NAND flash memory device as claimed in claim 2, further comprising a second bank status indicator configured to indicate that the second NAND flash memory bank is being utilized during the second page program operation on the second NAND flash memory bank.

4. The NAND flash memory device as claimed in claim 1 wherein the first bank status indicator configured to indicate that the first NAND flash memory bank is ready when the page program operation on the first NAND flash memory bank is completed.

5. The NAND flash memory device as claimed in claim 3 wherein the second bank status indicator configured to indicate that the second NAND flash memory bank is ready when the second page program operation on the second NAND flash memory bank is completed.

6. The NAND flash memory device as claimed in claim 3 wherein the second page program operation on the second NAND flash memory bank is performed during a time period that at least overlaps with a time period for the page program operation on the first NAND flash memory bank.

7. The NAND flash memory device as claimed in claim 1 wherein the at least two NAND flash memory banks are multi-level-cell (MLC) NAND flash memory.

8. The NAND flash memory device as claimed in claim 1 wherein the NAND flash memory device is comprised of multi-chip package configuration having two or more stacked chips inside a single package.

9. The NAND flash memory device as claimed in claim 8 wherein the two or more stacked chips are commonly coupled to the chip select input.

10. The NAND flash memory device as claimed in claim 1 wherein the page data is comprised of a data field and a spare field.

11. The NAND flash memory device as claimed in claim 1 wherein the common input is a single-bit data input.

12. The NAND flash memory device as claimed in claim 1 wherein the common input is a multi-byte data input.

13. The NAND flash memory device as claimed in claim 1 wherein the common input is comprised of a plurality of data input ports.

14. The NAND flash memory device as claimed in claim 1 wherein a transitioning of the first of the two control signals from an inactive state to the active state indicates a beginning of the command data being received at the common input.

15. A non-volatile memory system comprising:

a memory controller communicatively coupled to at least one NAND flash memory device, and the memory controller being configured to provide a command data, an address data and a page data to the at least one NAND flash memory device; and

the at least one NAND flash memory device comprising;

at least two NAND flash memory banks being independently operable by having respective control circuitry, row decoding circuitry, sense amplifier circuitry and page buffer circuitry;

a chip select input configured to receive a chip select signal;

a clock input configured to receive a clock signal;

a common command, address, data input configured to receive, all at different times, command data, address data and page data while the chip select signal is at an active low logic state, wherein the address data is including bank address data to identify the first NAND flash memory bank as addressed for performing a page program operation carried out thereon;

a first control input configured to receive a first of two control signals;

a second control input configured to receive a second of the two control signals;

circuitry configured to execute the page program operation on the first NAND flash memory bank corresponding to the command data;

a first bank status indicator configured to indicate that the first NAND flash memory bank is being utilized during the page program operation on the first NAND flash memory bank; and

latch circuitry configured to;

latch the command data while only the first of the two control signals is held at an active high logic state for at least a duration of time that the command data is received at the common input, and

latch the page data in synchronization with both rising and falling edges of the clock signal.

16. The non-volatile memory system as claimed in claim 15 wherein the common input is configured to receive, all at different times, second command data, second address data and second page data while the chip select signal is at the active low logic state and the first NAND flash memory bank is being utilized, wherein the second address data is including second bank address data to identify the second NAND flash memory bank as addressed for performing a second page program operation carried out thereon.

17. The non-volatile memory system as claimed in claim 16, wherein the at least one NAND flash memory device further comprising a second bank status indicator configured to indicate that the second NAND flash memory bank is being utilized during the second page program operation on the second NAND flash memory bank.

18. The non-volatile memory system as claimed in claim 15 wherein the first bank status indicator configured to indicate that the first NAND flash memory bank is ready when the page program operation on the first NAND flash memory bank is completed.

19. The non-volatile memory system as claimed in claim 17 wherein the second bank status indicator configured to indicate that the second NAND flash memory bank is ready when the second page program operation on the second NAND flash memory bank is completed.

20. The non-volatile memory system as claimed in claim 17 wherein the second page program operation on the second NAND flash memory bank is performed during a time period that at least overlaps with a time period for the page program operation on the first NAND flash memory bank.

21. The non-volatile memory system as claimed in claim 15 wherein the at least two NAND flash memory banks are multi-level-cell (MLC) NAND flash memory.

22. The non-volatile memory system as claimed in claim 15 wherein the NAND flash memory device is comprised of multi-chip package configuration having two or more stacked chips inside a single package.

23. The non-volatile memory system as claimed in claim 22 wherein the two or more stacked chips are commonly coupled to the chip select input.

24. The non-volatile memory system as claimed in claim 15 wherein the page data is comprised of a data field and a spare field.

25. The non-volatile memory system as claimed in claim 15 wherein the common input is a single-bit data input.

26. The non-volatile memory system as claimed in claim 15 wherein the common input is a multi-bit data input.

27. The non-volatile memory system as claimed in claim 15 wherein the common input is comprised of a plurality of data input ports.

28. The non-volatile memory system as claimed in claim 15 wherein a transitioning of the first of the two control signals from an inactive state to the active state indicates a beginning of the command data being received at the common input.