Phase change memory device

• US 9,779,805 B2
• Filed: 06/22/2015
• Issued: 10/03/2017
• Est. Priority Date: 07/27/2006
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Pellizzer, Fabio, Bez, Roberto, Bedeschi, Ferdinando, Gastaldi, Roberto
• Primary Examiner(s): Huang, Min
• Application Number:
  US14/746,483
• Publication Number:
  US 20150287458A1
• Time in Patent Office: 834 Days
• Field of Search: 36518907
• CPC Class Codes: G11C 11/56 using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
• CPC Class Codes: G11C 11/5678 using amorphous/crystalline phase transition storage elements
• CPC Class Codes: G11C 13/0004 comprising amorphous/crystalline phase transition cells
• CPC Class Codes: G11C 13/004 Reading or sensing circuits or methods
• CPC Class Codes: G11C 13/0069 Writing or programming circuits or methods
• CPC Class Codes: G11C 2013/0054 Read is performed on a reference element, e.g. cell, and the reference sensed value is used to compare the sensed value of the selected cell
• CPC Class Codes: G11C 2213/79 Array wherein the access device being a transistor
• CPC Class Codes: H10B 63/24 of the Ovonic threshold switching type
• CPC Class Codes: H10B 63/80 Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays
• CPC Class Codes: H10N 70/20 Multistable switching devices, e.g. memristors
• CPC Class Codes: H10N 70/231 based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect
• CPC Class Codes: H10N 70/826 adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
• CPC Class Codes: H10N 70/8413 adapted for resistive heating
• CPC Class Codes: H10N 70/8825 Selenides, e.g. GeSe
• CPC Class Codes: H10N 70/8828 Tellurides, e.g. GeSbTe

Abstract

A phase change memory device with memory cells (2) formed by a phase change memory element (3) and a selection switch (4). A reference cell (2a) formed by an own phase change memory element (3) and an own selection switch (4) is associated to a group (7) of memory cells to be read. An electrical quantity of the group of memory cells is compared with an analogous electrical quantity of the reference cell, thereby compensating any drift in the properties of the memory cells.

Claims

1. A method of reading a memory device, the method comprising:

sequentially coupling each of a plurality of reference cells to at least one of a plurality of comparators, each of a plurality of memory cell data bit lines being coupled to only one of the plurality of comparators, each of the plurality of reference cells being coupled to one of a plurality of reference cell bit lines and further being in a common row line with only a respective one of a plurality of memory cells to which it is being compared, each of the reference cells being programmed to a pre-defined threshold voltage corresponding to a respective reference value; and

comparing an electrical behavior of each of the plurality of memory cells and of the sequentially coupled ones of the plurality of reference cells to determine a value of respective ones of the plurality of memory cells being read.

2. The method of claim 1, further comprising accounting for a drift in a resistance value of each of the plurality of memory cells by programming an associated one of the plurality of reference cells proximate in time to a programming operation of a respective one of the plurality of memory cells.

3. The method of claim 1, further comprising:

applying a bias voltage to at least one of the plurality of memory cell data bit lines coupled to respective ones of the plurality of memory cells to be read within a row line; and

simultaneously supplying the bias voltage to selected ones of the plurality of reference cell bit lines coupled to selected ones of the plurality of reference cells within the row line.

4. The method of claim 3, further comprising:

detecting a switching of each of the plurality of reference cells;

terminating applying the bias voltage; and

reading the state of each of the respective ones of the plurality of memory cells.

5. The method of claim 3, comprising introducing a delay between detecting a switching of each of the plurality of reference cells and terminating applying a biasing voltage.

6. The method of claim 3, further comprising selecting the bias voltage to be a generally increasing voltage.

7. The method of claim 3, further comprising selecting the bias voltage to be a ramp voltage.

8. The method of claim 1, further comprising programming each of the plurality of reference cells to a pre-defined threshold voltage corresponding to a respective reference value.

9. A system, comprising:

a memory array having a plurality of phase change memory elements arranged in groups with each group being couplable to a respective row line, selected ones of the plurality of phase change memory elements further being coupled to a respective bit line, each bit line being coupled to only one of a plurality of comparators;

a first plurality of reference phase change memory elements each coupled to one of a plurality of reference cell bit lines, the first plurality of reference phase change memory elements being couplable to a respective one of the groups through the respective row line and to at least one of the plurality of comparators; and

a reading stage couplable to the memory array through reference column line switches to provide current from one of the plurality of reference phase change memory elements coupled to a specific one of the respective row lines during a read operation occurring in the respective row line, the reference column line switches being configured to be activated in sequence.

10. The system of claim 9, wherein each of the first plurality of reference phase change memory elements has a substantially same structure as the plurality of phase change memory elements within the respective group.

11. The system of claim 9, wherein a number of the first plurality of reference phase change memory elements is equivalent to the number of respective row lines.

12. The system of claim 9, further comprising a current/voltage converter within the reading stage that is couplable to data column lines and reference column lines through respective data column line switches and reference column line switches.

13. The system of claim 9, further comprising a second plurality of reference phase change memory elements in each group, a number within the second plurality of reference phase change memory elements being equivalent to a number of possible states to which the memory cells are programmable.

14. The system of claim 13, wherein each of the second plurality of reference phase change memory elements within each of the specific row lines is respectively programmed to a first intermediate state, a second intermediate state, and a set state.

15. A memory array, comprising:

a plurality of phase change memory elements arranged in rows and columns, the plurality of phase change memory elements further being arranged in groups where each group is couplable to a respective row line, each of the columns of the plurality of phase change memory elements in a column being coupled to one of a plurality of data column lines, the plurality of data column lines each coupled to one of a plurality of comparators; and

a plurality of reference cells each coupled to one of a plurality of reference column lines and each including a reference phase change memory element and a reference selecting element to couple sequentially each of a respective one of the plurality of reference cells to a reference column line and to at least one of the plurality of comparators, at least one of the plurality of reference cells being arranged in proximity to each of the groups and couplable only to the respective row line for the group, each of the plurality of reference cells being programmed to a pre-defined threshold voltage corresponding to a respective reference value.

16. The memory array of claim 15, further comprising a reading stage couplable to the memory array and having a current/voltage converter couplable to selected ones of the plurality of data column lines and selected ones of the reference column lines coupled to respective ones of the plurality of phase change memory elements.

17. The memory array of claim 16, wherein the reading stage includes a threshold detecting means selectively coupled to the plurality of reference cells to detect an electrical quantity of respective ones of the plurality of reference cells reaching a threshold.

18. The memory array of claim 16, wherein the reading stage further comprises:

a biasing voltage generator to apply a biasing voltage to the data bitlines and the reference column lines; and

a switching detector to couple selectively to the reference column lines to detect a switching of ones of the plurality of reference cells, the switching detector to generate a deactivation command for the biasing voltage generator when detecting switching of the ones of the plurality of reference cells.

19. The memory array of claim 18, wherein the biasing voltage generator comprises a voltage source and a plurality of cascode transistors that are controllably couplable to the voltage source, each of the plurality of cascode transistors being further controllably couplable to a respective one of the data column lines and the reference column lines.

20. The memory array of claim 15, further comprising each of the plurality of phase change memory elements having a data selecting element to couple a respective one of the plurality of phase change memory elements to a data column line.