Non-volatile static random access memory devices and methods of operations
First Claim
Patent Images
1. A non-volatile static random access memory (NVSRAM) device with a single semiconductor non-volatile memory element, comprising:
- an SRAM element comprising;
a latch having a first output node and a second output node for retaining a data bit; and
two access transistors whose gates are connected together to form a word line, one of the two access transistors being connected between the first output node and one of a bit line pair, the other access transistor being connected between the second output node and the other of the bit line pair; and
the single semiconductor non-volatile memory element being a single-transistor type consisting of four terminals which are a first source/drain electrode, and a second source/drain electrode, a control gate electrode and a body electrode, wherein the first source/drain electrode is connected to a voltage line only and the second source/drain electrode is directly connected to both one of the two output nodes and one of the two access transistors without any switching transistor connected between the voltage line and the one of the two output nodes;
wherein a predetermined datum is written to the latch from the bit line pair to cause the one of the output nodes to have a default voltage by turning on the two access transistors, the latch and the single semiconductor non-volatile memory element are isolated from the bit line pair by turning off the two access transistors, one of a ground voltage and an operating voltage of the SRAM element is applied to the voltage line, and an intermediate voltage is applied to a control gate of the single semiconductor non-volatile memory element to enable the non-volatile data bit stored in the single semiconductor non-volatile memory element to be written to the SRAM element; and
wherein the intermediate voltage is between a first threshold voltage and a second threshold voltage of the single semiconductor non-volatile memory element.
2 Assignments
0 Petitions
Accused Products
Abstract
Non-Volatile Static Random Access Memory (NVSRAM) cell devices applying only one single non-volatile element embedded in a conventional Static Random Access Memory (SRAM) cell are disclosed. The NVSRAM cell devices can be integrated into a compact cell array. The NVSRAM devices of the invention have a read/write speed of a conventional SRAM and non-volatile property of a non-volatile memory cell. The methods of operations for the NVSRAM devices of the invention are also disclosed.
-
Citations
14 Claims
-
1. A non-volatile static random access memory (NVSRAM) device with a single semiconductor non-volatile memory element, comprising:
-
an SRAM element comprising; a latch having a first output node and a second output node for retaining a data bit; and two access transistors whose gates are connected together to form a word line, one of the two access transistors being connected between the first output node and one of a bit line pair, the other access transistor being connected between the second output node and the other of the bit line pair; and the single semiconductor non-volatile memory element being a single-transistor type consisting of four terminals which are a first source/drain electrode, and a second source/drain electrode, a control gate electrode and a body electrode, wherein the first source/drain electrode is connected to a voltage line only and the second source/drain electrode is directly connected to both one of the two output nodes and one of the two access transistors without any switching transistor connected between the voltage line and the one of the two output nodes; wherein a predetermined datum is written to the latch from the bit line pair to cause the one of the output nodes to have a default voltage by turning on the two access transistors, the latch and the single semiconductor non-volatile memory element are isolated from the bit line pair by turning off the two access transistors, one of a ground voltage and an operating voltage of the SRAM element is applied to the voltage line, and an intermediate voltage is applied to a control gate of the single semiconductor non-volatile memory element to enable the non-volatile data bit stored in the single semiconductor non-volatile memory element to be written to the SRAM element; and wherein the intermediate voltage is between a first threshold voltage and a second threshold voltage of the single semiconductor non-volatile memory element. - View Dependent Claims (2, 3, 4, 5)
-
-
6. A method of loading an non-volatile storing data bit from a single semiconductor non-volatile memory element into an SRAM element in a non-volatile static random access memory (NVSRAM) device with the single semiconductor non-volatile memory element, the SRAM element comprising a latch and two access transistors, the latch having a first output node and a second output node, gates of the two access transistors being connected together to form a word line, one of the two access transistors being connected between the first output node and one of a bit line pair, the other access transistor being connected between the second output node and the other of the bit line pair, the single semiconductor non-volatile memory element being a single-transistor type consisting of four terminals which are a first source/drain electrode, a second source/drain electrode, a control gate electrode and a body electrode, wherein the first source/drain electrode is connected to a voltage line only and the second source/drain electrode is directly connected to both a connecting node and one of the two access transistors without any switching transistor connected between the voltage line and the connecting node, the connecting node being one of the two output nodes, the method comprising:
-
writing a predetermined datum to the latch from the bit line pair to cause the connecting node to have a default voltage by turning on the two access transistors; isolating the latch and the single semiconductor non-volatile memory element from the bit line pair by turning off the two access transistors; applying one of a ground voltage and an operating voltage of the SRAM element to the voltage line; and applying an intermediate voltage to a control gate of the single semiconductor non-volatile memory element to enable the non-volatile data bit stored in the single semiconductor non-volatile memory element to be written to the SRAM element; wherein the intermediate voltage is between a first threshold voltage and a second threshold voltage of the single semiconductor non-volatile memory element. - View Dependent Claims (7, 8, 9, 10, 11, 12, 13, 14)
-
Specification