Adaptation of high-order read thresholds

• US 9,779,818 B2
• Filed: 07/09/2015
• Issued: 10/03/2017
• Est. Priority Date: 07/09/2015
• Status: Active Grant

• Current Assignee: Apple Inc.
• Original Assignee: Apple Inc.
• Inventors: Baum, Barak, Radinski, Alex, Gurgi, Eyal, Sommer, Naftali, Kamelo, Tsafrir
• Primary Examiner(s): Kerveros, James C
• Application Number:
  US14/794,862
• Publication Number:
  US 20170011803A1
• Time in Patent Office: 817 Days
• Field of Search: 714763
• CPC Class Codes: G06F 11/1012 using codes or arrangements adapted for a specific type of error G06F11/1048 takes precedence
• CPC Class Codes: G11C 11/56 using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 11/5642 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/28 using differential sensing or reference cells, e.g. dummy cells
• CPC Class Codes: G11C 16/3418 Disturbance prevention or evaluation; Refreshing of disturbed memory data
• CPC Class Codes: G11C 16/3459 Circuits or methods to verify correct programming of nonvolatile memory cells
• CPC Class Codes: G11C 2029/0409 Online test
• CPC Class Codes: G11C 27/005 with non-volatile charge storage, e.g. on floating gate or MNOS
• CPC Class Codes: G11C 29/021 in voltage or current generators
• CPC Class Codes: G11C 29/028 with adaption or trimming of parameters
• CPC Class Codes: G11C 29/42 using error correcting codes [ECC] or parity check
• CPC Class Codes: G11C 7/14 Dummy cell management; Sense reference voltage generators

Abstract

A method includes storing data in memory cells by programming the memory cells with respective values. The memory cells are read in multiple readout operations that each compares the programmed values to at least first and second read thresholds, while keeping the first read threshold fixed throughout the readout operations and perturbing only the second read threshold between the readout operations. A preferred value for the second read threshold is estimated based on the multiple readout operations.

Claims

1. An apparatus, comprising:

an interface configured to communicate with a memory, wherein the memory comprises;

a memory array comprising multiple word lines, each having multiple memory cells; and

a read circuit, which is coupled to the memory array and is configured to convert analog values stored in the memory cells into digital samples by comparing the analog values to at least first and second read thresholds; and

circuitry, configured to;

instruct the read circuit to store data in the memory cells;

instruct the read circuit to read the memory cells in a sequence of multiple readout operations that advances sequentially over the word lines, wherein each of the multiple readout operations in the sequence reads the memory cells of a subsequent word line;

throughout the multiple readout operations, instruct the read circuit to keep the first read threshold fixed and to perturb only the second read threshold between the multiple readout operations from the different word lines; and

estimate a preferred value for the second read threshold based on the multiple readout operations.

2. The apparatus according to claim 1, wherein the circuitry is configured to estimate multiple respective threshold-accuracy metrics for the readout operations, and to estimate the preferred value based on the threshold-accuracy metrics.

3. A method, comprising:

storing data in a memory, wherein the memory comprises;

a memory array comprising multiple word lines, each having multiple memory cells; and

a read circuit, which is coupled to the memory array and is configured to convert analog values stored in the memory cells into digital samples by comparing the analog values to at least first and second read thresholds;

instructing the read circuit to read the memory cells in a sequence of multiple readout operations that advances sequentially over the word lines, wherein each of the multiple readout operations in the sequence reads the memory cells of a subsequent word line;

throughout the multiple readout operations, instructing the read circuit to keep the first read threshold fixed and to perturb only the second read threshold between the readout operations from the different word lines; and

estimating a preferred value for the second read threshold based on the multiple readout operations.

4. The method according to claim 3, wherein the multiple readout operations comprise normal readout operations that read data in response to requests from a host.

5. The method according to claim 3, wherein estimating the preferred value for the second read threshold comprises estimating respective threshold-accuracy metrics for the readout operations, and estimating the preferred value based on the threshold-accuracy metrics.

6. The method according to claim 5, wherein estimating the threshold-accuracy metrics comprises assessing a respective number of read errors occurring in each of the readout operations.

7. The method according to claim 5, wherein storing the data comprises encoding the data with an Error Correction Code (ECC) that is defined by a set of check equations, and wherein estimating the threshold-accuracy metrics comprises assessing a respective number of the check equations that are satisfied by readout results of each of the readout operations.

8. The method according to claim 5, wherein storing the data comprises encoding the data with an Error Correction Code (ECC), wherein instructing the read circuit to read the memory cells comprises decoding the ECC in a sequence of decoding iterations, and wherein estimating the threshold-accuracy metrics comprises assessing a respective number of the decoding iterations performed in each of the readout operations.

9. The method according to claim 5, wherein storing the data comprises encoding the data with an Error Correction Code (ECC), wherein instructing the read circuit to read the memory cells comprises decoding the ECC using a decoding scheme selected from multiple possible decoding schemes, and wherein estimating the threshold-accuracy metrics comprises assessing the decoding scheme selected in each of the readout operations.

10. The method according to claim 5, wherein estimating the threshold-accuracy metrics comprises assessing a first number of bit errors corrected from “

1”

to “

0”

, and a second number of bit errors corrected from “

0”

to “

1”

.

11. The method according to claim 5, wherein estimating the preferred value comprises choosing a direction in which to adjust the second read threshold between readout operations from different word lines, based on the threshold-accuracy metrics.

12. The method according to claim 5, wherein estimating the preferred value comprises choosing an increment size by which to adjust the second read threshold between readout operations from different word lines, based on the threshold-accuracy metrics.

13. The method according to claim 3, wherein storing the data comprises mapping data values to programmed values in accordance with a mapping in which the programmed values representing different data values are distinguishable by two or more read thresholds.

14. An apparatus, comprising:

an interface configured to communicate with a memory, wherein the memory comprises;

a memory array comprising multiple word lines, each having multiple memory cells; and

a read circuit, which is coupled to the memory array and is configured to convert analog values stored in the memory cells into digital samples by comparing the analog values to at least first and second read thresholds; and

circuitry, configured to;

store data in the memory cells;

instruct the read circuit to read the data from the memory cells, in response to a request for the data, in a sequence of multiple readout operations that advances sequentially over the word lines, wherein each of the multiple readout operations in the sequence reads the memory cells of a subsequent word line while perturbing the read threshold between the readout operations from the different word lines; and

estimate a preferred value for the read threshold based on the multiple readout operations.

15. The apparatus according to claim 14, wherein the circuitry is configured to estimate respective threshold-accuracy metrics for the readout operations, and to estimate the preferred value based on the threshold-accuracy metrics.

16. A method, comprising:

storing data in a memory, wherein the memory comprises;

a memory array comprising multiple word lines, each having multiple memory cells; and

a read circuit, which is coupled to the memory array and is configured to convert analog values stored in the memory cells into digital samples by comparing the analog values to at least first and second read thresholds;

in response to a request for the data, instructing the read circuit to read the data from the memory cells in a sequence of multiple readout operations that advances sequentially over the word lines, wherein each of the multiple readout operations in the sequence reads the memory cells of a subsequent word line while perturbing the read threshold between the readout operations from the different word lines; and

estimating a preferred value for the read threshold based on the multiple readout operations.

17. The method according to claim 16, wherein estimating the preferred value for the read threshold comprises estimating respective threshold-accuracy metrics for the readout operations, and estimating the preferred value based on the threshold-accuracy metrics.

18. The method according to claim 17, wherein estimating the threshold-accuracy metrics comprises assessing a respective number of read errors occurring in each of the readout operations.

19. The method according to claim 17, wherein storing the data comprises encoding the data with an Error Correction Code (ECC) that is defined by a set of check equations, and wherein estimating the threshold-accuracy metrics comprises assessing a respective number of the check equations that are satisfied by readout results of each of the readout operations.

20. The method according to claim 17, wherein storing the data comprises encoding the data with an Error Correction Code (ECC), wherein instructing the read circuit to read the memory cells comprises decoding the ECC in a sequence of decoding iterations, and wherein estimating the threshold-accuracy metrics comprises assessing a respective number of the decoding iterations performed in each of the readout operations.

21. The method according to claim 17, wherein storing the data comprises encoding the data with an Error Correction Code (ECC), wherein instructing the read circuit to read the memory cells comprises decoding the ECC using a decoding scheme selected from multiple possible decoding schemes, and wherein estimating the threshold-accuracy metrics comprises assessing the decoding scheme selected in each of the readout operations.

22. The method according to claim 17, wherein estimating the threshold-accuracy metrics comprises assessing a first number of bit errors corrected from “

1”

to “

0”

, and a second number of bit errors corrected from “

0”

to “

1”

.

23. The method according to claim 17, wherein estimating the preferred value comprises choosing a direction in which to adjust the read threshold between readout operations from different word lines, based on the threshold-accuracy metrics.

24. The method according to claim 17, wherein estimating the preferred value comprises choosing an increment size by which to adjust the read threshold between readout operations from different word lines, based on the threshold-accuracy metrics.